From nobody Sun Feb 8 09:07:39 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5198325481; Thu, 16 Oct 2025 12:07:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616454; cv=pass; b=CaGrL46KQ5GDClAmrNe/RLQPxyP/BIPAGugrKAp2oElC96RdhIF7iPetLNmrzutTQTrfoypzwuqdSE9H0K5vWCUUwVoJBGp1EL0unwrinhuxaFRJBegX8bDkCmbrr+c4u9v29f2qOalqSPqquHoY92e03RuHSrQ3AnjVVzm/W9c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616454; c=relaxed/simple; bh=RWNR7pbRYbVrt/PWXx+/flTl5EUt4ZglyZfA1Myr3c0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pJLVYswYibN/U+Ye314t03AW+o+2VglXRj01Vg5kVRuJT2/aYJToUqJTQsUCFpZ8RRvFJskCP83yRcAGu3yOtgVyuV26wlJT60NXxFUEF5UY0m0THIn0uWu0577xYH9yWY621CTcotKYwe/zDn/MbkFIRDoEPu2V6PAMIcyd4jY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=OeavtJKb; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="OeavtJKb" ARC-Seal: i=1; a=rsa-sha256; t=1760616422; cv=none; d=zohomail.com; s=zohoarc; b=UPujpThNFaHKsmdKu1jpvuVS+IzfvaWarhnDA5R5h6HYJOkL2G58kAMaGJRc6VBZXSC0VwRYic4yXRlX8xPt89Sz+AQrdFAhzAi+jARFg4xGEJ5d11j3OWJBJkc0Tvf9fYGQk0eCBb+fB+e4v9Zv1M/mMfWv1R7nsCmQsbKw+Gg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760616422; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=837Jh8zhwTRC7cY1zr6WrqRr5pWTWPvsURbryj0OQa8=; b=ltojfJKkmY82Q+J1xfeM0SWQe/USoCuDfioL3/isAz587J+raZ7EQ2B5wE8uBwtirmlp8izaBo3MgUTsv0KPQJ1FgvhfwKCgwnSi7NK2J2vZt4UTgnZmMBefb/ZQhmzOtwB8wTKsHIM28R8ze7Uk9sXVlGEg11HtiBng1XHx5GA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760616422; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=837Jh8zhwTRC7cY1zr6WrqRr5pWTWPvsURbryj0OQa8=; b=OeavtJKbz3xFSLvvhQgJ8XPMHjJn3/QHczFk16BxEXjJgPngIRHpxGt0dc6AJdZT doM4aITyuKXoOUBdkV4ygYrpY1MnCXlgkrAhkzoe8d5jlplDYasAFSvUtVqADR2Gpvz 3/1U4ho/y1lh9OpZEYnGDNaWCL/nB36xXFuojW10= Received: by mx.zohomail.com with SMTPS id 1760616420498761.5807558630529; Thu, 16 Oct 2025 05:07:00 -0700 (PDT) From: Nicolas Frattaroli Date: Thu, 16 Oct 2025 14:06:43 +0200 Subject: [PATCH v2 1/5] dt-bindings: ufs: mediatek,ufs: Add mt8196-ufshci variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-1-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek MT8196 SoC contains the same UFS host controller interface hardware as the MT8195 SoC. Add it as a variant of MT8195, and extend its list of allowed clocks, as well as give it the previously absent resets property. Also add examples for both MT8195 and the new MT8196, so that the binding can be verified against examples for these two variants. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 134 +++++++++++++++++= ++-- 1 file changed, 123 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 1dec54fb00f3..070ae0982591 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -11,18 +11,30 @@ maintainers: =20 properties: compatible: - enum: - - mediatek,mt8183-ufshci - - mediatek,mt8192-ufshci - - mediatek,mt8195-ufshci + oneOf: + - enum: + - mediatek,mt8183-ufshci + - mediatek,mt8195-ufshci + - items: + - enum: + - mediatek,mt8192-ufshci + - const: mediatek,mt8183-ufshci + - items: + - enum: + - mediatek,mt8196-ufshci + - const: mediatek,mt8195-ufshci =20 clocks: minItems: 1 - maxItems: 8 + maxItems: 16 =20 clock-names: minItems: 1 - maxItems: 8 + maxItems: 16 + + freq-table-hz: true + + interrupts: true =20 phys: maxItems: 1 @@ -30,7 +42,15 @@ properties: reg: maxItems: 1 =20 + resets: + maxItems: 3 + + reset-names: + maxItems: 3 + vcc-supply: true + vccq-supply: true + vccq2-supply: true =20 mediatek,ufs-disable-mcq: $ref: /schemas/types.yaml#/definitions/flag @@ -44,22 +64,19 @@ required: - reg - vcc-supply =20 -unevaluatedProperties: false - allOf: - $ref: ufs-common.yaml - - if: properties: compatible: contains: - enum: - - mediatek,mt8195-ufshci + const: mediatek,mt8195-ufshci then: properties: clocks: minItems: 8 clock-names: + minItems: 8 items: - const: ufs - const: ufs_aes @@ -69,6 +86,19 @@ allOf: - const: unipro_mp_bclk - const: ufs_tx_symbol - const: ufs_mem_sub + - const: crypt_mux + - const: crypt_lp + - const: crypt_perf + - const: ufs_sel + - const: ufs_sel_min_src + - const: ufs_sel_max_src + - const: ufs_rx_symbol0 + - const: ufs_rx_symbol1 + reset-names: + items: + - const: unipro_rst + - const: crypto_rst + - const: hci_rst else: properties: clocks: @@ -76,6 +106,10 @@ allOf: clock-names: items: - const: ufs + resets: false + reset-names: false + +unevaluatedProperties: false =20 examples: - | @@ -99,3 +133,81 @@ examples: vcc-supply =3D <&mt_pmic_vemc_ldo_reg>; }; }; + - | + ufshci@11270000 { + compatible =3D "mediatek,mt8195-ufshci"; + reg =3D <0x11270000 0x2300>; + interrupts =3D ; + phys =3D <&ufsphy>; + clocks =3D <&infracfg_ao 63>, <&infracfg_ao 64>, <&infracfg_ao 65>, + <&infracfg_ao 54>, <&infracfg_ao 55>, + <&infracfg_ao 56>, <&infracfg_ao 90>, + <&infracfg_ao 93>; + clock-names =3D "ufs", "ufs_aes", "ufs_tick", + "unipro_sysclk", "unipro_tick", + "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub"; + freq-table-hz =3D <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>, <0 0>, + <0 0>, <0 0>; + vcc-supply =3D <&mt6359_vemc_1_ldo_reg>; + mediatek,ufs-disable-mcq; + }; + - | + #include + #include + + ufshci@16810000 { + compatible =3D "mediatek,mt8196-ufshci", "mediatek,mt8195-ufshci"; + reg =3D <0x16810000 0x2a00>; + interrupts =3D ; + + clocks =3D <&ufs_ao_clk 6>, + <&ufs_ao_clk 7>, + <&clk26m>, + <&ufs_ao_clk 3>, + <&clk26m>, + <&ufs_ao_clk 4>, + <&ufs_ao_clk 0>, + <&topckgen 7>, + <&topckgen 41>, + <&topckgen 105>, + <&topckgen 83>, + <&topckgen 42>, + <&topckgen 84>, + <&topckgen 102>, + <&ufs_ao_clk 1>, + <&ufs_ao_clk 2>; + clock-names =3D "ufs", + "ufs_aes", + "ufs_tick", + "unipro_sysclk", + "unipro_tick", + "unipro_mp_bclk", + "ufs_tx_symbol", + "ufs_mem_sub", + "crypt_mux", + "crypt_lp", + "crypt_perf", + "ufs_sel", + "ufs_sel_min_src", + "ufs_sel_max_src", + "ufs_rx_symbol0", + "ufs_rx_symbol1"; + + freq-table-hz =3D <273000000 499200000>, <0 0>, <0 0>, <0 0>, <0 0= >, + <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <= 0 0>, + <0 0>; + + phys =3D <&ufsphy>; + + vcc-supply =3D <&mt6363_vemc>; + vccq-supply =3D <&mt6363_vufs12>; + vccq2-supply =3D <&mt6363_vufs18>; + + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>; + reset-names =3D "unipro_rst", "crypto_rst", "hci_rst"; + mediatek,ufs-disable-mcq; + }; --=20 2.51.0 From nobody Sun Feb 8 09:07:39 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A84A331CA54; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-2-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek MT8196 SoC includes an M-PHY compatible with the already existing mt8183 binding. However, one omission from the original binding was that all of these variants may have an optional reset. Add the new compatible, and also the resets property, with an example. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Peter Wang --- .../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/= Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml index 3e62b5d4da61..f414aaa18997 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - mediatek,mt8195-ufsphy + - mediatek,mt8196-ufsphy - const: mediatek,mt8183-ufsphy - const: mediatek,mt8183-ufsphy =20 @@ -42,6 +43,10 @@ properties: - const: unipro - const: mp =20 + resets: + items: + - description: Optional UFS M-PHY reset. + "#phy-cells": const: 0 =20 @@ -65,5 +70,16 @@ examples: clock-names =3D "unipro", "mp"; #phy-cells =3D <0>; }; + - | + #include + ufs-phy@16800000 { + compatible =3D "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy"; + reg =3D <0x16800000 0x10000>; + clocks =3D <&ufs_ao_clk 3>, + <&ufs_ao_clk 5>; + clock-names =3D "unipro", "mp"; + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>; + #phy-cells =3D <0>; + }; =20 ... --=20 2.51.0 From nobody Sun Feb 8 09:07:39 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CE231CA54; Thu, 16 Oct 2025 12:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616471; cv=pass; b=StOxMFlmEbOOfF/WtRYvSDX6o+0EVDngX8XreYUl0JHUqokssX3ECPADFNG48x+Wr0Um+jJ6bb5iPgKNfUyPn8ep+M6PCPjR6OMh0afaTijiK4Cobe9wtN9J8DSQRK2Xm93UJwwX+tEKnY+vctdmM5JWE2O+KqzEDZL0u8VsCks= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760616471; c=relaxed/simple; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=GqKYMqqQwg166HBFvWGr1lohoFtGyKjc7tuyv5xhFJQ=; b=KUqFRsGHHbHdAyNduyeRrVB+7MkRNXgaG8+axbmKFVJfl0cHMuZnYIEMddbLhShI MwM+41oe9xHpo7QCtB6hcoPL5C8jY7PBwzwihxI9zosq/uEeAVZn/Rl8+zXlGCyuePw yvtYMNgiv8bIogaMlaeB1ewUYhm2lq8wz0WsLeaI= Received: by mx.zohomail.com with SMTPS id 1760616432172550.8290009089878; Thu, 16 Oct 2025 05:07:12 -0700 (PDT) From: Nicolas Frattaroli Date: Thu, 16 Oct 2025 14:06:45 +0200 Subject: [PATCH v2 3/5] scsi: ufs: mediatek: Move MTK_SIP_UFS_CONTROL to mtk_sip_svc.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-3-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 SMC commands used by multiple drivers need to live in a shared header file somewhere to avoid code duplication. In order to rework the MPHY reset control to be in the phy-mtk-ufs.c driver, both ufs-mediatek and the phy driver need access to this command. Move it to mtk_sip_svc.h, where other such command definitions already live. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Peter Wang --- drivers/ufs/host/ufs-mediatek-sip.h | 1 - include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index 7d17aedf6fb8..d627dfb4a766 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -11,7 +11,6 @@ /* * SiP (Slicon Partner) commands */ -#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/m= ediatek/mtk_sip_svc.h index abe24a73ee19..7265ff2a6e2a 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,6 +22,9 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) =20 +/* UFS related SMC call */ +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) + /* DVFSRC SMC calls */ #define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506) =20 --=20 2.51.0 From nobody Sun Feb 8 09:07:39 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1379C32BF54; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-4-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek UFS PHY supports PHY resets. Until now, they've been implemented in the UFS host driver. Since they were never documented in the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if it's moved to the correct location, which is the PHY driver. Implement the MPHY reset logic in this driver and expose it through the phy subsystem's reset op. The reset itself is optional, as judging by other mainline devices that use this hardware, it's not required for the device to function. If no reset is present, the reset op returns -EOPNOTSUPP, which means that the ufshci driver can detect it's present and not double sleep in its own reset function, where it will call the phy reset. Reviewed-by: Philipp Zabel Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Peter Wang --- drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-= mtk-ufs.c index 0cb5a25b1b7a..d77ba689ebc8 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -4,6 +4,7 @@ * Author: Stanley Chu */ =20 +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include =20 #include "phy-mtk-io.h" =20 @@ -36,9 +39,17 @@ =20 #define UFSPHY_CLKS_CNT 2 =20 +#define UFS_MTK_SIP_MPHY_CTRL BIT(8) + +enum ufs_mtk_mphy_op { + UFS_MPHY_BACKUP =3D 0, + UFS_MPHY_RESTORE +}; + struct ufs_mtk_phy { struct device *dev; void __iomem *mmio; + struct reset_control *reset; struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; =20 @@ -141,9 +152,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_p= hy) return 0; } =20 +static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op = op) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op, + 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + default: + return 0; + } +} + +static int ufs_mtk_phy_reset(struct phy *generic_phy) +{ + struct ufs_mtk_phy *phy =3D get_ufs_mtk_phy(generic_phy); + int ret; + + if (!phy->reset) + return -EOPNOTSUPP; + + ret =3D reset_control_assert(phy->reset); + if (ret) + return ret; + + usleep_range(100, 110); + + ret =3D reset_control_deassert(phy->reset); + if (ret) + return ret; + + /* + * To avoid double-sleep and other unintended side-effects in the ufshci + * driver, don't return the phy_ctrl retval here, but just return -EPROTO. + */ + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE); + if (ret) { + dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n", + ERR_PTR(ret)); + return -EPROTO; + } + + return 0; +} + static const struct phy_ops ufs_mtk_phy_ops =3D { .power_on =3D ufs_mtk_phy_power_on, .power_off =3D ufs_mtk_phy_power_off, + .reset =3D ufs_mtk_phy_reset, .owner =3D THIS_MODULE, }; =20 @@ -163,8 +224,18 @@ static int ufs_mtk_phy_probe(struct platform_device *p= dev) if (IS_ERR(phy->mmio)) return PTR_ERR(phy->mmio); =20 + phy->reset =3D devm_reset_control_get_optional(dev, NULL); + if (IS_ERR(phy->reset)) + return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n"); + phy->dev =3D dev; =20 + if (phy->reset) { + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP); + if (ret) + return dev_err_probe(dev, ret, "Failed to back up MPHY\n"); + } + ret =3D ufs_mtk_phy_clk_init(phy); if (ret) return ret; --=20 2.51.0 From nobody Sun Feb 8 09:07:39 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 041DD324B3B; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760616444; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=7UJzWh8Mx5huqt0Mv4EI6oIxF7/UV+tu1eGThaILPpw=; b=bT4Nhvf87bjJhpTCYG+2b0iurXRZQIEjlN+hpuBl8Mie1btFDBAUAOWgupXJcMl8 00uFK2Zn6tbgd5TKc6zc7tXFetc1OsqHuiSFiHbxp2djyuK8IIR9Pi8YRI8eNMax00X 7HxtjmNvndRgjl2X+Izm6cA7e4sa0LdP97H29r8I= Received: by mx.zohomail.com with SMTPS id 1760616443593700.2604768184038; Thu, 16 Oct 2025 05:07:23 -0700 (PDT) From: Nicolas Frattaroli Date: Thu, 16 Oct 2025 14:06:47 +0200 Subject: [PATCH v2 5/5] scsi: ufs: mediatek: Rework resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-mt8196-ufs-v2-5-c373834c4e7a@collabora.com> References: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> In-Reply-To: <20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Rework the reset control getting in the driver's probe function to use the bulk reset APIs. Use the optional variant instead of defaulting to NULL if the resets fail, so that absent resets can be distinguished from erroneous resets. Also move all remnants of the MPHY reset ever having lived in this driver. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Peter Wang Reviewed-by: Philipp Zabel --- drivers/ufs/host/ufs-mediatek-sip.h | 8 ---- drivers/ufs/host/ufs-mediatek.c | 78 ++++++++++++++++++---------------= ---- drivers/ufs/host/ufs-mediatek.h | 7 ++-- 3 files changed, 42 insertions(+), 51 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index d627dfb4a766..256598cc3b5b 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num { UFS_VCC_MAX }; =20 -enum ufs_mtk_mphy_op { - UFS_MPHY_BACKUP =3D 0, - UFS_MPHY_RESTORE -}; - /* * SMC call wrapper function */ @@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version) =20 -#define ufs_mtk_mphy_ctrl(op, res) \ - ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op) - #define ufs_mtk_mtcmos_ctrl(op, res) \ ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op) =20 diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 758a393a9de1..5239ca4a428b 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -94,6 +94,12 @@ static const char *const ufs_uic_dl_err_str[] =3D { "PA_INIT" }; =20 +static const char *const ufs_reset_names[] =3D { + "unipro_rst", + "crypto_rst", + "hci_rst", +}; + static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -204,49 +210,45 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) static void ufs_mtk_host_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct arm_smccc_res res; - - reset_control_assert(host->hci_reset); - reset_control_assert(host->crypto_reset); - reset_control_assert(host->unipro_reset); - reset_control_assert(host->mphy_reset); - - usleep_range(100, 110); + int ret; =20 - reset_control_deassert(host->unipro_reset); - reset_control_deassert(host->crypto_reset); - reset_control_deassert(host->hci_reset); - reset_control_deassert(host->mphy_reset); + ret =3D reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret)); =20 - /* restore mphy setting aftre mphy reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res); -} + ret =3D phy_reset(host->mphy); =20 -static void ufs_mtk_init_reset_control(struct ufs_hba *hba, - struct reset_control **rc, - char *str) -{ - *rc =3D devm_reset_control_get(hba->dev, str); - if (IS_ERR(*rc)) { - dev_info(hba->dev, "Failed to get reset control %s: %ld\n", - str, PTR_ERR(*rc)); - *rc =3D NULL; + /* + * Only sleep if MPHY doesn't have a reset implemented (which already + * sleeps) or the PHY reset function failed somehow, just to be safe + */ + if (ret) { + usleep_range(100, 110); + if (ret !=3D -EOPNOTSUPP) + dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret)); } + + ret =3D reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret)); } =20 -static void ufs_mtk_init_reset(struct ufs_hba *hba) +static int ufs_mtk_init_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + int ret, i; + + for (i =3D 0; i < MTK_UFS_NUM_RESETS; i++) + host->resets[i].id =3D ufs_reset_names[i]; =20 - ufs_mtk_init_reset_control(hba, &host->hci_reset, - "hci_rst"); - ufs_mtk_init_reset_control(hba, &host->unipro_reset, - "unipro_rst"); - ufs_mtk_init_reset_control(hba, &host->crypto_reset, - "crypto_rst"); - ufs_mtk_init_reset_control(hba, &host->mphy_reset, - "mphy_rst"); + ret =3D devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_= NUM_RESETS, + host->resets); + if (ret) { + dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret)); + return ret; + } + + return 0; } =20 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, @@ -1238,11 +1240,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) if (err) goto out_variant_clear; =20 - ufs_mtk_init_reset(hba); - - /* backup mphy setting if mphy can reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res); + err =3D ufs_mtk_init_reset(hba); + if (err) + goto out_variant_clear; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index dfbf78bd8664..c020fe04fe9e 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -7,12 +7,14 @@ #define _UFS_MEDIATEK_H =20 #include +#include =20 /* * MCQ define and struct */ #define UFSHCD_MAX_Q_NR 8 #define MTK_MCQ_INVALID_IRQ 0xFFFF +#define MTK_UFS_NUM_RESETS 3 =20 /* REG_UFS_MMIO_OPT_CTRL_0 160h */ #define EHS_EN BIT(0) @@ -171,10 +173,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_va09; - struct reset_control *hci_reset; - struct reset_control *unipro_reset; - struct reset_control *crypto_reset; - struct reset_control *mphy_reset; + struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; struct ufs_mtk_clk mclk; --=20 2.51.0