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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b5ccccb4811sm549021666b.56.2025.10.16.08.58.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 08:58:51 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 16 Oct 2025 16:58:42 +0100 Subject: [PATCH v3 09/10] pmdomain: samsung: add support for google,gs101-pd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-gs101-pd-v3-9-7b30797396e7@linaro.org> References: <20251016-gs101-pd-v3-0-7b30797396e7@linaro.org> In-Reply-To: <20251016-gs101-pd-v3-0-7b30797396e7@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Marek Szyprowski Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 On Google gs101, direct mmio register access to the PMU registers doesn't work and access must happen via a (syscon) regmap created by the PMU driver instead. Try to obtain this regmap using the parent node in DT in case this PD is a child of the PMU and fall back to the traditional direct mmio regmap otherwise. Additionally, the status is just one bit on gs101. Signed-off-by: Andr=C3=A9 Draszik --- drivers/pmdomain/samsung/exynos-pm-domains.c | 65 +++++++++++++++++++-----= ---- 1 file changed, 45 insertions(+), 20 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 15a1582aa92103a07335eb681600d9415369fefd..a7e55624728a62545eac049c9a5= 1012a229f44c2 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -78,8 +79,15 @@ static const struct exynos_pm_domain_config exynos5433_c= fg =3D { .need_early_sync_state =3D true, }; =20 +static const struct exynos_pm_domain_config gs101_cfg =3D { + .local_pwr_cfg =3D BIT(0), +}; + static const struct of_device_id exynos_pm_domain_of_match[] =3D { { + .compatible =3D "google,gs101-pd", + .data =3D &gs101_cfg, + }, { .compatible =3D "samsung,exynos4210-pd", .data =3D &exynos4210_cfg, }, { @@ -107,17 +115,9 @@ static int exynos_pd_probe(struct platform_device *pde= v) struct of_phandle_args child, parent; struct exynos_pm_domain *pd; struct resource *res; - void __iomem *base; unsigned int val; int on, ret; =20 - struct regmap_config reg_config =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .use_relaxed_mmio =3D true, - }; - pm_domain_cfg =3D of_device_get_match_data(dev); pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); if (!pd) @@ -128,25 +128,50 @@ static int exynos_pd_probe(struct platform_device *pd= ev) return -ENOMEM; =20 /* - * The resource typically points into the address space of the PMU. + * The resource typically points into the address space of the PMU and + * we have to consider two cases: + * 1) some implementations require a custom syscon regmap + * 2) this driver might map the same addresses as the PMU driver * Therefore, avoid using devm_platform_get_and_ioremap_resource() and - * instead use platform_get_resource() and devm_ioremap() to avoid + * instead use platform_get_resource() here, and below for case 1) use + * syscon_node_to_regmap() while for case 2) use devm_ioremap() to avoid * conflicts due to address space overlap. */ res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return dev_err_probe(dev, -ENXIO, "missing IO resources"); =20 - base =3D devm_ioremap(dev, res->start, resource_size(res)); - if (!base) - return dev_err_probe(dev, -ENOMEM, - "failed to ioremap PMU registers"); - - reg_config.max_register =3D resource_size(res) - reg_config.reg_stride; - pd->regmap =3D devm_regmap_init_mmio(dev, base, ®_config); - if (IS_ERR(pd->regmap)) - return dev_err_probe(dev, PTR_ERR(base), - "failed to init regmap"); + if (dev->parent && + of_device_is_compatible(dev->parent->of_node, "syscon")) { + pd->regmap =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pd->regmap)) + return dev_err_probe(dev, PTR_ERR(pd->regmap), + "failed to acquire PMU regmap"); + + pd->configuration_reg =3D res->start; + pd->status_reg =3D res->start; + } else { + void __iomem *base; + + const struct regmap_config reg_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .use_relaxed_mmio =3D true, + .max_register =3D (resource_size(res) + - reg_config.reg_stride), + }; + + base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return dev_err_probe(dev, -ENOMEM, + "failed to ioremap PMU registers"); + + pd->regmap =3D devm_regmap_init_mmio(dev, base, ®_config); + if (IS_ERR(pd->regmap)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to init regmap"); + } =20 pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; --=20 2.51.0.788.g6d19910ace-goog