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[34.34.48.254]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b5ccccb4811sm549021666b.56.2025.10.16.08.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 08:58:45 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 16 Oct 2025 16:58:38 +0100 Subject: [PATCH v3 05/10] pmdomain: samsung: convert to using regmap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251016-gs101-pd-v3-5-7b30797396e7@linaro.org> References: <20251016-gs101-pd-v3-0-7b30797396e7@linaro.org> In-Reply-To: <20251016-gs101-pd-v3-0-7b30797396e7@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Marek Szyprowski Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 On platforms such as Google gs101, direct mmio register access to the PMU registers doesn't necessarily work and access must happen via a (syscon) regmap created by the PMU driver instead. In preparation for supporting such SoCs convert the existing mmio accesses to using a regmap wrapper. With this change in place, a follow-up patch can update the driver to optionally acquire the PMU-created regmap without having to change the rest of the code. Signed-off-by: Andr=C3=A9 Draszik --- There is one checkpatch warning, relating to the non-const regmap_config. It can not easily be made const at this stage, but a follow-up patch allows us to make it const and the warning will go away anyway. --- drivers/pmdomain/samsung/exynos-pm-domains.c | 78 ++++++++++++++++++++----= ---- 1 file changed, 57 insertions(+), 21 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index f53e1bd2479807988f969774b4b7b4c5739c1aba..383126245811cb8e4dbae3b99ce= d3f06d3093f35 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -9,15 +9,14 @@ // conjunction with runtime-pm. Support for both device-tree and non-devic= e-tree // based power domain support is included. =20 -#include #include #include #include #include #include #include -#include #include +#include =20 struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ @@ -28,7 +27,7 @@ struct exynos_pm_domain_config { * Exynos specific wrapper around the generic power domain */ struct exynos_pm_domain { - void __iomem *base; + struct regmap *regmap; struct generic_pm_domain pd; u32 local_pwr_cfg; }; @@ -36,31 +35,37 @@ struct exynos_pm_domain { static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { struct exynos_pm_domain *pd; - void __iomem *base; u32 timeout, pwr; - char *op; + int err; =20 pd =3D container_of(domain, struct exynos_pm_domain, pd); - base =3D pd->base; =20 pwr =3D power_on ? pd->local_pwr_cfg : 0; - writel_relaxed(pwr, base); + err =3D regmap_write(pd->regmap, 0, pwr); + if (err) + return err; =20 /* Wait max 1ms */ timeout =3D 10; - - while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) !=3D pwr) { - if (!timeout) { - op =3D (power_on) ? "enable" : "disable"; - pr_err("Power domain %s %s failed\n", domain->name, op); - return -ETIMEDOUT; + while (timeout-- > 0) { + unsigned int val; + + err =3D regmap_read(pd->regmap, 0x4, &val); + if (err || ((val & pd->local_pwr_cfg) !=3D pwr)) { + cpu_relax(); + usleep_range(80, 100); + continue; } - timeout--; - cpu_relax(); - usleep_range(80, 100); + + return 0; } =20 - return 0; + if (!err) + err =3D -ETIMEDOUT; + pr_err("Power domain %s %sable failed: %d\n", domain->name, + power_on ? "en" : "dis", err); + + return err; } =20 static int exynos_pd_power_on(struct generic_pm_domain *domain) @@ -109,8 +114,18 @@ static int exynos_pd_probe(struct platform_device *pde= v) struct device_node *np =3D dev->of_node; struct of_phandle_args child, parent; struct exynos_pm_domain *pd; + struct resource *res; + void __iomem *base; + unsigned int val; int on, ret; =20 + struct regmap_config reg_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .use_relaxed_mmio =3D true, + }; + pm_domain_cfg =3D of_device_get_match_data(dev); pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); if (!pd) @@ -120,15 +135,36 @@ static int exynos_pd_probe(struct platform_device *pd= ev) if (!pd->pd.name) return -ENOMEM; =20 - pd->base =3D of_iomap(np, 0); - if (!pd->base) - return -ENODEV; + /* + * The resource typically points into the address space of the PMU. + * Therefore, avoid using devm_platform_get_and_ioremap_resource() and + * instead use platform_get_resource() and devm_ioremap() to avoid + * conflicts due to address space overlap. + */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return dev_err_probe(dev, -ENXIO, "missing IO resources"); + + base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return dev_err_probe(dev, -ENOMEM, + "failed to ioremap PMU registers"); + + reg_config.max_register =3D resource_size(res) - reg_config.reg_stride; + pd->regmap =3D devm_regmap_init_mmio(dev, base, ®_config); + if (IS_ERR(pd->regmap)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to init regmap"); =20 pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; pd->local_pwr_cfg =3D pm_domain_cfg->local_pwr_cfg; =20 - on =3D readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; + ret =3D regmap_read(pd->regmap, 0x4, &val); + if (ret) + return dev_err_probe(dev, ret, "failed to read status"); + + on =3D val & pd->local_pwr_cfg; =20 pm_genpd_init(&pd->pd, NULL, !on); ret =3D of_genpd_add_provider_simple(np, &pd->pd); --=20 2.51.0.788.g6d19910ace-goog