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Wed, 15 Oct 2025 16:17:08 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b6a2288786bsm733067a12.5.2025.10.15.16.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 16:17:08 -0700 (PDT) From: Samuel Holland To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi Cc: Samuel Holland , Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH] PCI: dwc: Use multiple ATU regions for large bridge windows Date: Wed, 15 Oct 2025 16:15:01 -0700 Message-ID: <20251015231707.3862179-1-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some SoCs may allocate more address space for a bridge window than can be covered by a single ATU region. Allow using a larger bridge window by allocating multiple adjacent ATU regions. Signed-off-by: Samuel Holland Acked-by: Charles Mirabile Reviewed-by: Frank Li --- An example of where this is needed is the ESWIN EIC7700 SoC[1]. The SoC decodes 128 GiB of address space to the PCIe controller. Without this change, only 8 GiB is usable; after this change 48 GiB (6 ATU regions) is usable, which allows using PCIe cards with >8 GiB BARs: eic7700-pcie 54000000.pcie: host bridge /soc/pcie@54000000 ranges: eic7700-pcie 54000000.pcie: IO 0x0040800000..0x0040ffffff -> 0x004080= 0000 eic7700-pcie 54000000.pcie: MEM 0x0041000000..0x004fffffff -> 0x004100= 0000 eic7700-pcie 54000000.pcie: MEM 0x8000000000..0x89ffffffff -> 0x800000= 0000 eic7700-pcie 54000000.pcie: iATU: unroll T, 8 ob, 4 ib, align 4K, limit 8G eic7700-pcie 54000000.pcie: PCIe Gen.2 x1 link up eic7700-pcie 54000000.pcie: PCI host bridge to bus 0000:00 [1]: https://lore.kernel.org/linux-pci/20250923120946.1218-1-zhangsenchuan@= eswincomputing.com/ .../pci/controller/dwc/pcie-designware-host.c | 34 ++++++++++++------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 20c9333bcb1c..148076331d7b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -873,30 +873,40 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->windows) { + u64 total_size; + if (resource_type(entry->res) !=3D IORESOURCE_MEM) continue; =20 - if (pci->num_ob_windows <=3D ++i) - break; - - atu.index =3D i; atu.type =3D PCIE_ATU_TYPE_MEM; atu.parent_bus_addr =3D entry->res->start - pci->parent_bus_offset; atu.pci_addr =3D entry->res->start - entry->offset; =20 /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent =3D=3D entry->res) - atu.size =3D resource_size(entry->res) - + total_size =3D resource_size(entry->res) - resource_size(pp->msg_res); else - atu.size =3D resource_size(entry->res); + total_size =3D resource_size(entry->res); =20 - ret =3D dw_pcie_prog_outbound_atu(pci, &atu); - if (ret) { - dev_err(pci->dev, "Failed to set MEM range %pr\n", - entry->res); - return ret; - } + do { + if (pci->num_ob_windows <=3D ++i) + break; + + atu.index =3D i; + atu.size =3D min(total_size, pci->region_limit + 1); + + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) { + dev_err(pci->dev, "Failed to set MEM range %pr\n", + entry->res); + return ret; + } + + atu.parent_bus_addr +=3D atu.size; + atu.pci_addr +=3D atu.size; + total_size -=3D atu.size; + } while (total_size); } =20 if (pp->io_size) { --=20 2.47.2 base-commit: 5a6f65d1502551f84c158789e5d89299c78907c7 branch: up/pci-bridge-window