From nobody Fri Dec 19 20:33:04 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5A6827EFEF for ; Wed, 15 Oct 2025 14:30:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538607; cv=none; b=B0JgCjIo1UtXBMlCFx/mK21vsqB5ezOjSCMi/eXSeFr95wPYYzMQFf4jLSCXxgoJJdQaL31/9EHkd2cfWtxIjLGu18iV9niPFkEKQxBoMlKim6J4vzzrra2+pxA6/8it/a2G2C1bQXSGQoM0latm6C6owEdkqnhTV/2GIrn/t/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538607; c=relaxed/simple; bh=JF5d0RuqHdzuzAyczJrD8nFHVpQJnUZyIUIRam1+8Hs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VC7tcbATFn9rgtnjJub13vj5pp9wkdS/AaQa73x7ADc4BIMORbT/C7VSjiJ6nbHjdgVsJpz/m+FPkUuKfkkUZBw5G7naBWxqQZh0OD5C0OXduPqDEoQ6L08ThfHQ4aL7n9df9psXcHQwU9XsTkKbz5uR2jtjjkE0nUKM9LtJqlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=I6smQ6fi; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="I6smQ6fi" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 41A12C09FB6; Wed, 15 Oct 2025 14:29:43 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5CD91606F9; Wed, 15 Oct 2025 14:30:02 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C55F9102F229E; Wed, 15 Oct 2025 16:29:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760538601; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=22T1dg1cbNfiO27ErLkrwh8WK9WMTDQ6TnjoQ7G7mW8=; b=I6smQ6fiRvw3h6Haj7ezxlNJWUUXuj20KrGzzFyZarvQRLsiF/+VGb0MIkOIPANjYK6k+3 F6KAgHv4zAnLkVxEjdSfYweAsEdz5K5C553E38Dq7ysr4dM7oywkL4rKuEmBi73VWm6xcU 7jfgzzZ/l+KyT5eQ71huXR6tom+M4Q7d0EnvW7qi4h90a7NcviSwKCpus6VTNbFFmIRsdI Usxw8duWPDXjlsEd9uYcHJQ+XTggzXQXv+908YAvhQYRMEp7FNS/2Q0+9ctUEh7HY2/yd8 +SIVXWVHLM8MGQEzub7w4TFxCy7Vu9T3orUDJDS3nOv3A6fQa0Tfwr5GDg5FZQ== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH 1/4] dt-bindings: iio: adc: Add the Renesas RZ/N1 ADC Date: Wed, 15 Oct 2025 16:28:13 +0200 Message-ID: <20251015142816.1274605-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015142816.1274605-1-herve.codina@bootlin.com> References: <20251015142816.1274605-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The Renesas RZ/N1 ADC controller is the ADC controller available in the Renesas RZ/N1 SoCs family. Signed-off-by: Herve Codina (Schneider Electric) --- .../bindings/iio/adc/renesas,rzn1-adc.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,rzn1-= adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yam= l b/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml new file mode 100644 index 000000000000..73a08eef28d9 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Analog to Digital Converter (ADC) + +maintainers: + - Herve Codina + +description: + The Renesas RZ/N1 ADC controller available in the Renesas RZ/N1 SoCs fam= ily + can use up to two internal ACD cores (ADC1 and ADC2) those internal core= s are + handled through ADC controller virtual channels. + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-adc # RZ/N1D + - const: renesas,rzn1-adc + + reg: + maxItems: 1 + + clocks: + items: + - description: APB internal bus clock + - description: ADC clock + + clock-names: + items: + - const: pclk + - const: adc-clk + + power-domains: + maxItems: 1 + + adc1-avdd-supply: + description: + ADC1 analog power supply. + + adc1-vref-supply: + description: + ADC1 reference voltage supply. + + adc2-avdd-supply: + description: + ADC2 analog power supply. + + adc2-vref-supply: + description: + ADC2 reference voltage supply. + + '#io-channel-cells': + const: 1 + description: | + Channels numbers available: + if ADC1 is used (i.e. adc1-{avdd,vref}-supply present): + - 0: ADC1 IN0 + - 1: ADC1 IN1 + - 2: ADC1 IN2 + - 3: ADC1 IN3 + - 4: ADC1 IN4 + - 5: ADC1 IN6 + - 6: ADC1 IN7 + - 7: ADC1 IN8 + if ADC2 is used (i.e. adc2-{avdd,vref}-supply present): + - 8: ADC2 IN0 + - 9: ADC2 IN1 + - 10: ADC2 IN2 + - 11: ADC2 IN3 + - 12: ADC2 IN4 + - 13: ADC2 IN6 + - 14: ADC2 IN7 + - 15: ADC2 IN8 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#io-channel-cells' + +dependencies: + # None or both adc1-avdd-supply / adc1-vref-supply should be present + adc1-avdd-supply: [ adc1-vref-supply ] + adc1-vref-supply: [ adc1-avdd-supply ] + # None or both adc2-avdd-supply / adc2-vref-supply should be present + adc2-avdd-supply: [ adc2-vref-supply ] + adc2-vref-supply: [ adc2-avdd-supply ] + +# At least one of avvd/vref supplies +anyOf: + - required: + - adc1-vref-supply + - adc1-avdd-supply + - required: + - adc2-vref-supply + - adc2-avdd-supply + +examples: + - | + #include + + adc: adc@40065000 { + compatible =3D "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg =3D <0x40065000 0x200>; + clocks =3D <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_AD= C>; + clock-names =3D "pclk", "adc-clk"; + power-domains =3D <&sysctrl>; + adc1-avdd-supply =3D <&adc1_avdd>; + adc1-vref-supply =3D <&adc1_vref>; + #io-channel-cells =3D <1>; + }; +... --=20 2.51.0 From nobody Fri Dec 19 20:33:04 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5AD827F19B; Wed, 15 Oct 2025 14:30:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538608; cv=none; b=q8STDwLPWZv4L8BmsFvbb179tPHS2fWtDjwQBAC8dfmKQuwPJw8ocxww45TcnS++udcTSeiHtgpUGCF8jukYe6nVF8I9/UsyXj4QC4cdCsO3LsGveiHwBzvz16XdW1qOcif+Lj+0kZNKuDyVMGIRRQtwW4PuKkyB1j3sL1jmM+M= ARC-Message-Signature: i=1; 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Wed, 15 Oct 2025 14:29:45 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 51285606F9; Wed, 15 Oct 2025 14:30:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CDBC4102F22BC; Wed, 15 Oct 2025 16:30:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760538603; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=83hzTyixmKMFHx2AzSVqY3Lz5W/qXSoAWTy3xhdjKDM=; b=F4hKe/jT13wT85A4gsgLvbyUbKSJV49Li4urTop9NCgZI3pnke7D7IZuXOXZkWYsb4l/oz NQHYXug/6Ultd/zFfWyZULIh/FXj8y+8qzfrmJQGHEtbrEiucSPIBFcwTGDMvObVGHhVpd LGLFA6w50b/N1GksLLwKh4M4H+YiNmpg8zxwQmV6l3XJQ+1OcxSpamj/v98ix5N913YX28 rCzFmoykW5qVYAFt7Uk/GHFVYTwGbrbaQ5iqWaAMATuQRiIPCac4AMHsDJG+fd+mXW3Pn0 9g2wP0DMwi5y+v7IJTPSMfEp9Cw1u3LYfaRjQlieLvvfq6uPhBI2GT/x2oNvVA== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH 2/4] iio: adc: Add support for the Renesas RZ/N1 ADC Date: Wed, 15 Oct 2025 16:28:14 +0200 Message-ID: <20251015142816.1274605-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015142816.1274605-1-herve.codina@bootlin.com> References: <20251015142816.1274605-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The Renesas RZ/N1 ADC controller is the ADC controller available in the Renesas RZ/N1 SoCs family. It can use up to two internal ACD cores (ADC1 and ADC2) those internal cores are not directly accessed but are handled through ADC controller virtual channels. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzn1-adc.c | 626 +++++++++++++++++++++++++++++++++++++ 3 files changed, 637 insertions(+) create mode 100644 drivers/iio/adc/rzn1-adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f6..113f6a5c9745 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1403,6 +1403,16 @@ config RZG2L_ADC To compile this driver as a module, choose M here: the module will be called rzg2l_adc. =20 +config RZN1_ADC + tristate "Renesas RZ/N1 ADC driver" + depends on ARCH_RZN1 || COMPILE_TEST + help + Say yes here to build support for the ADC found in Renesas + RZ/N1 family. + + To compile this driver as a module, choose M here: the + module will be called rzn1-adc. + config SC27XX_ADC tristate "Spreadtrum SC27xx series PMICs ADC" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d008f78dc010..ba7a8a63d070 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) +=3D rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) +=3D rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o +obj-$(CONFIG_RZN1_ADC) +=3D rzn1-adc.o obj-$(CONFIG_SC27XX_ADC) +=3D sc27xx_adc.o obj-$(CONFIG_SD_ADC_MODULATOR) +=3D sd_adc_modulator.o obj-$(CONFIG_SOPHGO_CV1800B_ADC) +=3D sophgo-cv1800b-adc.o diff --git a/drivers/iio/adc/rzn1-adc.c b/drivers/iio/adc/rzn1-adc.c new file mode 100644 index 000000000000..f5e16b9cdf17 --- /dev/null +++ b/drivers/iio/adc/rzn1-adc.c @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/N1 ADC driver + * + * Copyright (C) 2025 Schneider-Electric + * + * Author: Herve Codina + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ADC1 ADC2 + * RZ/N1D, BGA 400 y y + * RZ/N1D, BGA 324 y n + * RZ/N1S, BGA 324 y n + * RZ/N1S, BGA 196 y n + * RZ/N1L, BGA 196 y n + */ + +#define RZN1_ADC_CONTROL_REG 0x2c +#define RZN1_ADC_CONTROL_ADC_BUSY BIT(6) +#define RZN1_ADC_FORCE_REG 0x30 +#define RZN1_ADC_SET_FORCE_REG 0x34 +#define RZN1_ADC_CLEAR_FORCE_REG 0x38 +#define RZN1_ADC_FORCE_VC(_n) BIT(_n) + +#define RZN1_ADC_CONFIG_REG 0x40 +#define RZN1_ADC_CONFIG_ADC_POWER_DOWN BIT(3) + +#define RZN1_ADC_VC_REG(_n) (0xc0 + 0x4 * (_n)) +#define RZN1_ADC_VC_ADC2_ENABLE BIT(16) +#define RZN1_ADC_VC_ADC1_ENABLE BIT(15) +#define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK GENMASK(5, 3) +#define RZN1_ADC_VC_ADC2_CHANNEL_SEL(_c) FIELD_PREP(RZN1_ADC_VC_ADC2_CHANN= EL_SEL_MASK, _c) +#define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK GENMASK(2, 0) +#define RZN1_ADC_VC_ADC1_CHANNEL_SEL(_c) FIELD_PREP(RZN1_ADC_VC_ADC1_CHANN= EL_SEL_MASK, _c) + +#define RZN1_ADC_ADC1_DATA_REG(_n) (0x100 + 0x4 * (_n)) +#define RZN1_ADC_ADC2_DATA_REG(_n) (0x140 + 0x4 * (_n)) +#define RZN1_ADC_ADCX_DATA_DATA_MASK GENMASK(11, 0) +#define RZN1_ADC_ADCX_GET_DATA(_reg) FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MAS= K, _reg) + +#define RZN1_ADC_CHANNEL_SHARED_SCALE(_ch, _ds_name) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (_ch), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .datasheet_name =3D (_ds_name), \ +} + +#define RZN1_ADC_CHANNEL_SEPARATED_SCALE(_ch, _ds_name) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (_ch), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .datasheet_name =3D (_ds_name), \ +} + +/* + * 8 ADC1_IN signals existed numbered 0..4, 6..8 + * ADCx_IN5 doesn't exist in RZ/N1 datasheet + */ +static struct iio_chan_spec rzn1_adc1_channels[] =3D { + RZN1_ADC_CHANNEL_SHARED_SCALE(0, "ADC1_IN0"), + RZN1_ADC_CHANNEL_SHARED_SCALE(1, "ADC1_IN1"), + RZN1_ADC_CHANNEL_SHARED_SCALE(2, "ADC1_IN2"), + RZN1_ADC_CHANNEL_SHARED_SCALE(3, "ADC1_IN3"), + RZN1_ADC_CHANNEL_SHARED_SCALE(4, "ADC1_IN4"), + RZN1_ADC_CHANNEL_SHARED_SCALE(5, "ADC1_IN6"), + RZN1_ADC_CHANNEL_SHARED_SCALE(6, "ADC1_IN7"), + RZN1_ADC_CHANNEL_SHARED_SCALE(7, "ADC1_IN8"), +}; + +static struct iio_chan_spec rzn1_adc2_channels[] =3D { + RZN1_ADC_CHANNEL_SHARED_SCALE(8, "ADC2_IN0"), + RZN1_ADC_CHANNEL_SHARED_SCALE(9, "ADC2_IN1"), + RZN1_ADC_CHANNEL_SHARED_SCALE(10, "ADC2_IN2"), + RZN1_ADC_CHANNEL_SHARED_SCALE(11, "ADC2_IN3"), + RZN1_ADC_CHANNEL_SHARED_SCALE(12, "ADC2_IN4"), + RZN1_ADC_CHANNEL_SHARED_SCALE(13, "ADC2_IN6"), + RZN1_ADC_CHANNEL_SHARED_SCALE(14, "ADC2_IN7"), + RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"), +}; + +/* + * If both ADCs core are used, scale cannot be common. Indeed, scale is + * based on Vref connected on each ADC core. + */ +static struct iio_chan_spec rzn1_adc1_adc2_channels[] =3D { + RZN1_ADC_CHANNEL_SEPARATED_SCALE(0, "ADC1_IN0"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(1, "ADC1_IN1"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(2, "ADC1_IN2"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(3, "ADC1_IN3"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(4, "ADC1_IN4"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(5, "ADC1_IN6"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(6, "ADC1_IN7"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(7, "ADC1_IN8"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(8, "ADC2_IN0"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(9, "ADC2_IN1"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(10, "ADC2_IN2"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(11, "ADC2_IN3"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(12, "ADC2_IN4"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(13, "ADC2_IN6"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(14, "ADC2_IN7"), + RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"), +}; + +struct rzn1_adc_core { + int is_used; + struct regulator *avdd; + struct regulator *vref; +}; + +struct rzn1_adc { + struct device *dev; + void __iomem *regs; + struct mutex lock; /* ADC lock */ + struct clk *pclk; + struct clk *adc_clk; + struct rzn1_adc_core adc_core[2]; /* ADC1 and ADC2 */ +}; + +static int rzn1_adc_core_power_on(struct rzn1_adc_core *adc_core) +{ + int ret; + + if (!adc_core->is_used) + return 0; + + ret =3D regulator_enable(adc_core->avdd); + if (ret) + return ret; + + ret =3D regulator_enable(adc_core->vref); + if (ret) { + regulator_disable(adc_core->avdd); + return ret; + } + + return 0; +} + +static void rzn1_adc_core_power_off(struct rzn1_adc_core *adc_core) +{ + if (!adc_core->is_used) + return; + + regulator_disable(adc_core->avdd); + regulator_disable(adc_core->vref); +} + +static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc, + struct rzn1_adc_core *adc_core, + const char *avdd_name, const char *vref_name) +{ + struct device *dev =3D rzn1_adc->dev; + int ret; + + adc_core->avdd =3D devm_regulator_get_optional(dev, avdd_name); + if (IS_ERR(adc_core->avdd)) { + ret =3D PTR_ERR(adc_core->avdd); + if (ret !=3D -ENODEV) + return dev_err_probe(dev, ret, + "Failed to get '%s' regulator\n", + avdd_name); + adc_core->avdd =3D NULL; + } + + adc_core->vref =3D devm_regulator_get_optional(dev, vref_name); + if (IS_ERR(adc_core->vref)) { + ret =3D PTR_ERR(adc_core->vref); + if (ret !=3D -ENODEV) + return dev_err_probe(dev, ret, + "Failed to get '%s' regulator\n", + vref_name); + adc_core->vref =3D NULL; + } + + /* + * Both regulators (avdd and vref) need to be available to have the + * related adc_core used. + */ + adc_core->is_used =3D adc_core->vref && adc_core->avdd; + return 0; +} + +static int rzn1_adc_core_get_vref_mv(struct rzn1_adc_core *adc_core) +{ + int vref_uv; + + if (!adc_core->vref) + return -ENODEV; + + vref_uv =3D regulator_get_voltage(adc_core->vref); + if (vref_uv < 0) + return vref_uv; + + return vref_uv / 1000; +} + +static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power) +{ + u32 v; + + writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN, + rzn1_adc->regs + RZN1_ADC_CONFIG_REG); + + /* + * Wait for the ADC_BUSY to clear. + * + * On timeout, ret is -ETIMEDOUT, otherwise it will be 0. + */ + return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG, + v, !(v & RZN1_ADC_CONTROL_ADC_BUSY), + 0, 500); +} + +static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch, + int adc1_ch, int adc2_ch) +{ + u32 vc =3D 0; + + if (adc1_ch !=3D -1) + vc |=3D RZN1_ADC_VC_ADC1_ENABLE | RZN1_ADC_VC_ADC1_CHANNEL_SEL(adc1_ch); + + if (adc2_ch !=3D -1) + vc |=3D RZN1_ADC_VC_ADC2_ENABLE | RZN1_ADC_VC_ADC2_CHANNEL_SEL(adc2_ch); + + writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch)); +} + +static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch) +{ + u32 val; + + val =3D readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG); + if (val & RZN1_ADC_FORCE_VC(ch)) + return -EBUSY; + + writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG); + + return 0; +} + +static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch) +{ + writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG); +} + +static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch, + u32 *adc1_data, u32 *adc2_data) +{ + u32 data_reg; + int ret; + u32 v; + + /* + * When a VC is selected, it needs 20 ADC clocks to perform the + * conversion. + * + * The worst case is when the 16 VCs need to perform a conversion and + * our VC is the lowest in term of priority. + * + * In that case, the conversion is performed in 16 * 20 ADC clocks. + * + * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst + * case of 16 * 20 * 1/4Mhz =3D 80us. + * + * Round it up to 100us + */ + + /* + * Wait for the ADC_FORCE_VC(n) to clear. + * + * On timeout, ret is -ETIMEDOUT, otherwise it will be 0. + */ + ret =3D readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG, + v, !(v & RZN1_ADC_FORCE_VC(ch)), + 0, 100); + if (ret) + return ret; + + if (adc1_data) { + data_reg =3D readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch)); + *adc1_data =3D RZN1_ADC_ADCX_GET_DATA(data_reg); + } + + if (adc2_data) { + data_reg =3D readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch)); + *adc2_data =3D RZN1_ADC_ADCX_GET_DATA(data_reg); + } + + return 0; +} + +static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int ch= an, int *val) +{ + u32 *adc1_data, *adc2_data; + int adc1_ch, adc2_ch; + u32 adc_data; + int ret; + + if (chan < 8) { + /* chan 0..7 used to get ADC1 ch 0..7 */ + adc1_ch =3D chan; + adc1_data =3D &adc_data; + adc2_ch =3D -1; + adc2_data =3D NULL; + } else if (chan < 16) { + /* chan 8..15 used to get ADC2 ch 0..7 */ + adc1_ch =3D -1; + adc1_data =3D NULL; + adc2_ch =3D chan - 8; + adc2_data =3D &adc_data; + } else { + return -EINVAL; + } + + ret =3D pm_runtime_resume_and_get(rzn1_adc->dev); + if (ret < 0) + return ret; + + mutex_lock(&rzn1_adc->lock); + + rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch); + + ret =3D rzn1_adc_vc_start_conversion(rzn1_adc, chan); + if (ret) + goto end; + + ret =3D rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data); + if (ret) { + rzn1_adc_vc_stop_conversion(rzn1_adc, chan); + goto end; + } + + *val =3D adc_data; + ret =3D IIO_VAL_INT; + +end: + mutex_unlock(&rzn1_adc->lock); + + pm_runtime_mark_last_busy(rzn1_adc->dev); + pm_runtime_put_autosuspend(rzn1_adc->dev); + + return ret; +} + +static int rzn1_adc_get_vref_mv(struct rzn1_adc *rzn1_adc, unsigned int ch= an) +{ + struct rzn1_adc_core *adc_core; + + /* + * chan 0..7 use ADC1 ch 0..7. Vref related to ADC1 core + * chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core + */ + if (chan < 8) + adc_core =3D &rzn1_adc->adc_core[0]; + else if (chan < 16) + adc_core =3D &rzn1_adc->adc_core[1]; + else + return -EINVAL; + + return rzn1_adc_core_get_vref_mv(adc_core); +} + +static int rzn1_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_sp= ec const *chan, + int *val, int *val2, long mask) +{ + struct rzn1_adc *rzn1_adc =3D iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret =3D rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val); + if (ret) + return ret; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + ret =3D rzn1_adc_get_vref_mv(rzn1_adc, chan->channel); + if (ret < 0) + return ret; + *val =3D ret; + *val2 =3D 12; + return IIO_VAL_FRACTIONAL_LOG2; + + default: + break; + } + + return -EINVAL; +} + +static const struct iio_info rzn1_adc_info =3D { + .read_raw =3D &rzn1_adc_read_raw +}; + +static int rzn1_adc_enable(struct rzn1_adc *rzn1_adc) +{ + int ret; + + ret =3D rzn1_adc_core_power_on(&rzn1_adc->adc_core[0]); + if (ret) + return ret; + + ret =3D rzn1_adc_core_power_on(&rzn1_adc->adc_core[1]); + if (ret) + goto poweroff_adc_core0; + + ret =3D clk_prepare_enable(rzn1_adc->pclk); + if (ret) + goto poweroff_adc_core1; + + ret =3D clk_prepare_enable(rzn1_adc->adc_clk); + if (ret) + goto disable_pclk; + + ret =3D rzn1_adc_power(rzn1_adc, true); + if (ret) + goto disable_adc_clk; + + return 0; + +disable_adc_clk: + clk_disable_unprepare(rzn1_adc->adc_clk); +disable_pclk: + clk_disable_unprepare(rzn1_adc->pclk); +poweroff_adc_core1: + rzn1_adc_core_power_off(&rzn1_adc->adc_core[1]); +poweroff_adc_core0: + rzn1_adc_core_power_off(&rzn1_adc->adc_core[0]); + return ret; +} + +static void rzn1_adc_disable(struct rzn1_adc *rzn1_adc) +{ + rzn1_adc_power(rzn1_adc, false); + + clk_disable_unprepare(rzn1_adc->adc_clk); + clk_disable_unprepare(rzn1_adc->pclk); + + rzn1_adc_core_power_off(&rzn1_adc->adc_core[1]); + rzn1_adc_core_power_off(&rzn1_adc->adc_core[0]); +} + +static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc, + struct iio_dev *indio_dev) +{ + int adc_used; + + adc_used =3D rzn1_adc->adc_core[0].is_used ? 0x01 : 0x00; + adc_used |=3D rzn1_adc->adc_core[1].is_used ? 0x02 : 0x00; + + switch (adc_used) { + case 0x01: + indio_dev->channels =3D rzn1_adc1_channels; + indio_dev->num_channels =3D ARRAY_SIZE(rzn1_adc1_channels); + return 0; + case 0x02: + indio_dev->channels =3D rzn1_adc2_channels; + indio_dev->num_channels =3D ARRAY_SIZE(rzn1_adc2_channels); + return 0; + case 0x03: + indio_dev->channels =3D rzn1_adc1_adc2_channels; + indio_dev->num_channels =3D ARRAY_SIZE(rzn1_adc1_adc2_channels); + return 0; + default: + break; + } + + dev_err(rzn1_adc->dev, "Failed to set IIO channels, no ADC core used\n"); + return -ENODEV; +} + +static int rzn1_adc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct iio_dev *indio_dev; + struct rzn1_adc *rzn1_adc; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*rzn1_adc)); + if (!indio_dev) + return -ENOMEM; + + rzn1_adc =3D iio_priv(indio_dev); + rzn1_adc->dev =3D dev; + mutex_init(&rzn1_adc->lock); + + rzn1_adc->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rzn1_adc->regs)) + return PTR_ERR(rzn1_adc->regs); + + rzn1_adc->pclk =3D devm_clk_get(dev, "pclk"); + if (IS_ERR(rzn1_adc->pclk)) + return dev_err_probe(dev, PTR_ERR(rzn1_adc->pclk), "Failed to get pclk\n= "); + + rzn1_adc->adc_clk =3D devm_clk_get(dev, "adc-clk"); + if (IS_ERR(rzn1_adc->pclk)) + return dev_err_probe(dev, PTR_ERR(rzn1_adc->pclk), "Failed to get adc-cl= k\n"); + + ret =3D rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc_core[0], + "adc1-avdd", "adc1-vref"); + if (ret) + return ret; + + ret =3D rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc_core[1], + "adc2-avdd", "adc2-vref"); + if (ret) + return ret; + + platform_set_drvdata(pdev, indio_dev); + + indio_dev->name =3D dev_name(dev); + indio_dev->info =3D &rzn1_adc_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + ret =3D rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev); + if (ret) + return ret; + + ret =3D rzn1_adc_enable(rzn1_adc); + if (ret) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret =3D devm_iio_device_register(dev, indio_dev); + if (ret) + goto disable; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; + +disable: + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + pm_runtime_set_suspended(dev); + pm_runtime_dont_use_autosuspend(dev); + + rzn1_adc_disable(rzn1_adc); + return ret; +} + +static void rzn1_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev =3D platform_get_drvdata(pdev); + struct rzn1_adc *rzn1_adc =3D iio_priv(indio_dev); + + pm_runtime_disable(rzn1_adc->dev); + pm_runtime_set_suspended(rzn1_adc->dev); + pm_runtime_dont_use_autosuspend(rzn1_adc->dev); + + rzn1_adc_disable(rzn1_adc); +} + +static int rzn1_adc_pm_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct rzn1_adc *rzn1_adc =3D iio_priv(indio_dev); + + rzn1_adc_disable(rzn1_adc); + + return 0; +} + +static int rzn1_adc_pm_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct rzn1_adc *rzn1_adc =3D iio_priv(indio_dev); + + return rzn1_adc_enable(rzn1_adc); +} + +static const struct dev_pm_ops rzn1_adc_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(rzn1_adc_pm_runtime_suspend, rzn1_adc_pm_runtime_resum= e, NULL) +}; + +static const struct of_device_id rzn1_adc_of_match[] =3D { + { .compatible =3D "renesas,rzn1-adc" }, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, rzn1_adc_of_match); + +static struct platform_driver rzn1_adc_driver =3D { + .probe =3D rzn1_adc_probe, + .remove =3D rzn1_adc_remove, + .driver =3D { + .name =3D "rzn1-adc", + .of_match_table =3D of_match_ptr(rzn1_adc_of_match), + .pm =3D pm_ptr(&rzn1_adc_pm_ops), + }, +}; + +module_platform_driver(rzn1_adc_driver); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Fri Dec 19 20:33:04 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA2A327F73A; Wed, 15 Oct 2025 14:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538609; cv=none; b=V/7+Y+2CM7uQTQBn9F11pVQtrJqa8QvriS/ijHfc+78UvJ4j6Wh40bRjwkeUyw5RlqCZou2H9Ltt3brKNCjXfWR++d2un2RkOwmcIhVx7OoJndCzuBdZw2XpoTRqWsMXCWh6XpRto7/HWUQd3P5x6VJf14vZ0rkKcuNLnyQPAD0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538609; c=relaxed/simple; bh=+74GyJc9+OI2SVGARFkyM2gLYhgmnpB+FeCJMuuSkwU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Wed, 15 Oct 2025 14:30:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C32C6102F22BD; Wed, 15 Oct 2025 16:30:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760538605; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=1MTlS3wR1Q1h02kAZB6qYeyhSzxbvaTHAjx55R/rBto=; b=FpjD/eAHJnsLuu+zsjyVwvMJVbYfaBWlH+izpawdTUD+bMl9PaglfmhfFWOduZfC63t9nx Mosj6AK5Fma5syuYvi0JIJrjhTuofsGkGWxZaXxCvR2m8GfXXQeneQxmfxqEq1MBQMnMJC GvmZIZ0QH651FzogjMOgp7i4X44bDlzR5sRXbYMXUKXWKukPu1z0dRb7PxqGCHcBsX23I0 0qt+qM5Z5927aU3W7AeHBsd1xBv2V5DuL2LcZ4XOruljQjqpIL3FlB+AFprP7soBc/Bg5n VToqXRkrX/09iAgkuZxuV00zHvv1VYCEZAIHbdsRk9XYyO6Hkq6fVcB8fYQydw== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH 3/4] ARM: dts: renesas: r9a06g032: Add the ADC device Date: Wed, 15 Oct 2025 16:28:15 +0200 Message-ID: <20251015142816.1274605-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015142816.1274605-1-herve.codina@bootlin.com> References: <20251015142816.1274605-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The ADC available in the r9a06g032 SoC can use up to two internal ACD cores (ADC1 and ADC2) those internal cores are handled through ADC controller virtual channels. Describe this device. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 13a60656b044..2bc07372bafa 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -290,6 +290,16 @@ i2c2: i2c@40064000 { status =3D "disabled"; }; =20 + adc: adc@40065000 { + compatible =3D "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg =3D <0x40065000 0x200>; + clocks =3D <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names =3D "pclk", "adc-clk"; + power-domains =3D <&sysctrl>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + pinctrl: pinctrl@40067000 { compatible =3D "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg =3D <0x40067000 0x1000>, <0x51000000 0x480>; --=20 2.51.0 From nobody Fri Dec 19 20:33:04 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7DE299AAF for ; Wed, 15 Oct 2025 14:30:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538612; cv=none; b=ksAJ3uO/2MWm5N2wk6r9cU1su5gjLvdnEOOSGU20sQDxSxoNECvkJsaOwvGTwfFeYT9SVxe6MSvq1JwMXiBIkCEDwo5DL9Ry4M0Na+1/7r7z1c1f2rBXs1bJvIU8vUcvYj190Q839gfgxorLVjaa1U3mWsQPVH5vNSVEAk8IXyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760538612; c=relaxed/simple; bh=mX6DRCpwZu0oJ3WXBuBCHDc7vccUf0lA0M42o6jyDC4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nWQlYyQJKSxyW9yY6MeTkvb6w026FbUTfUjRKAuTgPaHnwVGteuZdnyzdXKMwVJG1qBxxXWRqAvopui4Eu1temfUsrKT7YCEBFVqojisiTzWrfEK3gWVJ30CgR1Tb6WyXDh3fYtx1+25w2vOcqr1WIcPGSpWphwQBAo2il98eJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LRnFLNeq; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LRnFLNeq" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B38044E410D6; Wed, 15 Oct 2025 14:30:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 83374606F9; Wed, 15 Oct 2025 14:30:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BA6D0102F22DD; Wed, 15 Oct 2025 16:30:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760538607; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=/PMFWi9CEOOJIMVm87BvUcgLHk/cuD8EQlZaMOLBNAg=; b=LRnFLNeqaCNc8NTfpMXiOmKh9UGqtz8JLDp0WBOk/+o707hqz8UhjfoE5F1NHCrBFrnCEQ TU8Yw+ANgUTTzffZMzrWLcxbfLppRuh30QY48kPrk1DL4S8Uifh3DawGIqRHO+PODniJd2 XoenisfdFXued0/1hKmnQ7n4NMep7sEw2SoXVF5KN7gWvG430/XiIlA6OEvsWjsYfe0a+5 tfpB2W2yfHGFytPCYbLPo5qqdz9TILrYwHsF/cVUpR2cF/l5YMdnpl9zPatbFqVXeDPiXL AZrhL8bvyqGvLMUrMleNZW8EXjrgMOryJlXnw1dblQPj+1DTOQFrbxgf9HCtDA== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Herve Codina , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH 4/4] MAINTAINERS: Add the Renesas RZ/N1 ADC driver entry Date: Wed, 15 Oct 2025 16:28:16 +0200 Message-ID: <20251015142816.1274605-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015142816.1274605-1-herve.codina@bootlin.com> References: <20251015142816.1274605-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" After contributing the driver, add myself as the maintainer for the Renesas RZ/N1 ADC driver. Signed-off-by: Herve Codina (Schneider Electric) --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..40af68e4c9e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21874,6 +21874,14 @@ F: include/dt-bindings/net/pcs-rzn1-miic.h F: include/linux/pcs-rzn1-miic.h F: net/dsa/tag_rzn1_a5psw.c =20 +RENESAS RZ/N1 ADC DRIVER +M: Herve Codina +L: linux-iio@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,rzn1-adc.yaml +F: drivers/iio/adc/rzn1-adc.c + RENESAS RZ/N1 DWMAC GLUE LAYER M: Romain Gantois S: Maintained --=20 2.51.0