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Wed, 15 Oct 2025 06:13:45 -0500 Received: from DFLE201.ent.ti.com (10.64.6.59) by DFLE204.ent.ti.com (10.64.6.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 15 Oct 2025 06:13:45 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE201.ent.ti.com (10.64.6.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 15 Oct 2025 06:13:45 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59FBDbHj1809909; Wed, 15 Oct 2025 06:13:42 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file Date: Wed, 15 Oct 2025 16:43:33 +0530 Message-ID: <20251015111344.3639415-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "cpsw3g" node in the SoC file "k3-am62-main.dtsi" and enable it in the board (or board include) files: a) k3-am62-lp-sk.dts b) k3-am62-phycore-som.dtsi c) k3-am625-beagleplay.dts d) k3-am625-sk-common.dtsi Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-2-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. - Based on feedback from Dominik Haller at: https://lore.kernel.org/r/df6acbfe5d30956ed66e2768fa595c36d2ebe98a.camel@= phytec.de/ cpsw has been enabled in k3-am62-phycore-som.dtsi arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++ arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi | 1 + 5 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index ecfba05fe5c2..89be21783e27 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -181,6 +181,10 @@ &sdhci1 { vqmmc-supply =3D <&vddshv_sdio>; }; =20 +&cpsw3g { + status =3D "okay"; +}; + &cpsw_port2 { status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 40fb3c9e674c..0fd23ee996a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -723,6 +723,8 @@ cpsw3g: ethernet@8000000 { dma-names =3D "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index eeca643fedbe..1265ec792b13 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -211,6 +211,7 @@ opp-1400000000 { &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>; + status =3D "okay"; }; =20 &cpsw_port1 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 7028d9835c4a..774178b9aa88 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -590,6 +590,7 @@ &cpsw3g { <&gbe_pmx_obsclk>; assigned-clocks =3D <&k3_clks 157 70>, <&k3_clks 157 20>; assigned-clock-parents =3D <&k3_clks 157 72>, <&k3_clks 157 22>; + status =3D "okay"; }; =20 &cpsw_port1 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am625-sk-common.dtsi index fe0b98e1d105..73a8882a650a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi @@ -212,6 +212,7 @@ &sdhci1 { &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + status =3D "okay"; }; =20 &cpsw_port2 { --=20 2.51.0