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Wed, 15 Oct 2025 06:13:45 -0500 Received: from DFLE201.ent.ti.com (10.64.6.59) by DFLE204.ent.ti.com (10.64.6.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 15 Oct 2025 06:13:45 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE201.ent.ti.com (10.64.6.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 15 Oct 2025 06:13:45 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59FBDbHj1809909; Wed, 15 Oct 2025 06:13:42 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file Date: Wed, 15 Oct 2025 16:43:33 +0530 Message-ID: <20251015111344.3639415-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "cpsw3g" node in the SoC file "k3-am62-main.dtsi" and enable it in the board (or board include) files: a) k3-am62-lp-sk.dts b) k3-am62-phycore-som.dtsi c) k3-am625-beagleplay.dts d) k3-am625-sk-common.dtsi Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-2-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. - Based on feedback from Dominik Haller at: https://lore.kernel.org/r/df6acbfe5d30956ed66e2768fa595c36d2ebe98a.camel@= phytec.de/ cpsw has been enabled in k3-am62-phycore-som.dtsi arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++ arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi | 1 + 5 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index ecfba05fe5c2..89be21783e27 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -181,6 +181,10 @@ &sdhci1 { vqmmc-supply =3D <&vddshv_sdio>; }; =20 +&cpsw3g { + status =3D "okay"; +}; + &cpsw_port2 { status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 40fb3c9e674c..0fd23ee996a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -723,6 +723,8 @@ cpsw3g: ethernet@8000000 { dma-names =3D "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index eeca643fedbe..1265ec792b13 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -211,6 +211,7 @@ opp-1400000000 { &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>; + status =3D "okay"; }; =20 &cpsw_port1 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 7028d9835c4a..774178b9aa88 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -590,6 +590,7 @@ &cpsw3g { <&gbe_pmx_obsclk>; assigned-clocks =3D <&k3_clks 157 70>, <&k3_clks 157 20>; assigned-clock-parents =3D <&k3_clks 157 72>, <&k3_clks 157 22>; + status =3D "okay"; }; =20 &cpsw_port1 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am625-sk-common.dtsi index fe0b98e1d105..73a8882a650a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi @@ -212,6 +212,7 @@ &sdhci1 { &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + status =3D "okay"; }; =20 &cpsw_port2 { --=20 2.51.0 From nobody Tue Dec 16 14:51:23 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D486431DDAB; Wed, 15 Oct 2025 11:14:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; 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Wed, 15 Oct 2025 06:13:49 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE206.ent.ti.com (157.170.170.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 15 Oct 2025 06:13:49 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59FBDbHk1809909; Wed, 15 Oct 2025 06:13:45 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 2/5] arm64: dts: ti: k3-am65: disable "mcu_cpsw" in SoC file and enable in board file Date: Wed, 15 Oct 2025 16:43:34 +0530 Message-ID: <20251015111344.3639415-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-am65-mcu.dtsi" and enable it in the board file "k3-am654-base-board.dts". Also, now that "mcu_cpsw" is disabled in the SoC file, disabling it in "k3-am65-iot2050-common.dtsi" is no longer required. Hence, remove the section corresponding to this change. Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-3-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 42ba3dab2fc1..a9a4e7401a49 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -457,10 +457,6 @@ &main_i2c3 { #size-cells =3D <0>; }; =20 -&mcu_cpsw { - status =3D "disabled"; -}; - &sdhci1 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index f6d9a5779918..74439e0c16a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -354,6 +354,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 0c42c486d83a..8c3f150f6a84 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -571,6 +571,7 @@ partition@3fe0000 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { --=20 2.51.0 From nobody Tue Dec 16 14:51:23 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC08231CA5E; Wed, 15 Oct 2025 11:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 15 Oct 2025 06:13:52 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE211.ent.ti.com (157.170.170.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 15 Oct 2025 06:13:52 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59FBDbHl1809909; Wed, 15 Oct 2025 06:13:49 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 3/5] arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable in board file Date: Wed, 15 Oct 2025 16:43:35 +0530 Message-ID: <20251015111344.3639415-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j7200-mcu-wakeup.dtsi" and enable it in the board file "k3-j7200-common-proc-board.dts". Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-4-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index f684ce6ad9ad..f03a15edf954 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -323,6 +323,7 @@ &wkup_gpio0 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 692c4745040e..fec1db8b133d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.51.0 From nobody Tue Dec 16 14:51:23 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E29F931D371; Wed, 15 Oct 2025 11:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760526847; cv=none; b=A17dJB6Oj0DneiPMbNAEoSz3p0sh1XFdPI+IKm7IFSavH922w3q9bt90asIz9/4n970pH00oBQMxU+ibyd7yDwrddwJ42gj35ue78jkwAkgtSduYOrg5aStKGgqRn6hY7jj1HfRb0O4CP3xL0THXT029lqvjfBdGd5JphjZ6fp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760526847; c=relaxed/simple; bh=O1eWCrC3NVrZVNKW8/8/8uwpMgp6tpjN2Gf2bFUpJbI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 15 Oct 2025 06:13:53 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 4/5] arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it in board file Date: Wed, 15 Oct 2025 16:43:36 +0530 Message-ID: <20251015111344.3639415-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j721e-mcu-wakeup.dtsi" and enable it in the board files: a) k3-j721e-beagleboneai64.dts b) k3-j721e-common-proc-board.dts c) k3-j721e-sk.dts Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-5-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. - Enabled cpsw in k3-j721e-beagleboneai64.dts and k3-j721e-sk.dts arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 352fb60e6ce8..9907ef641ffc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -663,6 +663,7 @@ adc { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 45311438315f..5906dfa97205 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -769,6 +769,7 @@ exp5: gpio@20 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 42a21398e389..d5e5e89be5e9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -551,6 +551,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 5e5784ef6f85..0c65c541b02b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1034,6 +1034,7 @@ &usb1 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { --=20 2.51.0 From nobody Tue Dec 16 14:51:23 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB1F131E0FE; Wed, 15 Oct 2025 11:14:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760526856; cv=none; b=jAit+aGVfZkGxyTw085Y6cFL0i2Qi2vyxUk7XWGXUZSIveJekdwUfQU7MtFAZENWhBE3Csd6Kqv5UFmv8AS8MQvLVmj07HrpXZkuJEwG+3YEn9svUdWwQz3ZTsSKcRwz2DXYoUDT/ewEnx15zk/1nSmZWIBzGwFY7KhBGOAH/EQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760526856; c=relaxed/simple; bh=OgizwtT1W1HTYdW7W6Q46N7j/FNsDV5aR/OdVxogSS0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 15 Oct 2025 06:13:56 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v4 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files Date: Wed, 15 Oct 2025 16:43:37 +0530 Message-ID: <20251015111344.3639415-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015111344.3639415-1-s-vadapalli@ti.com> References: <20251015111344.3639415-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j721s2-mcu-wakeup.dtsi" and enable it in the board files: a) k3-am68-phyboard-izar.dts b) k3-am68-sk-base-board.dts c) k3-j721s2-common-proc-board.dts Signed-off-by: Siddharth Vadapalli --- v3 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20251014125349.= 3408784-6-s-vadapalli@ti.com/ Changes since v3: - Rebased patch on next-20251014. - Based on feedback from Dominik Haller at: https://lore.kernel.org/r/df6acbfe5d30956ed66e2768fa595c36d2ebe98a.camel@= phytec.de/ cpsw has been enabled in k3-am68-phyboard-izar.dts arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts | 1 + arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 4 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/= boot/dts/ti/k3-am68-phyboard-izar.dts index 41c8f8526e15..381880cf9d79 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts @@ -422,6 +422,7 @@ &main_uart8 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; + status =3D "okay"; }; =20 &mcu_i2c1 { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 75a107456ce1..e44542b1584c 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -692,6 +692,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 9e43dcff8ef2..3740596576c0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -457,6 +457,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 837097751c18..2a7f9c519735 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.51.0