From nobody Mon Oct 20 09:21:48 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B918936CE14 for ; Wed, 15 Oct 2025 18:14:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760552089; cv=none; b=Oy8pIsBzEJqVZGzHPpAu2lgt3+IRpHpvYOY+/EIUo0xYAjgxA+yRVNeoQeoJrHWtQNVhdk0Ft67ypgMjIECb+VqVBM5TtkFIrpBCxlREAjtFTQGN1bJfPcGGVtSkChKpFH+7wjceV7G3xYe27SQQw9Xbv0rBmooXd9Kuc1g//Ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760552089; c=relaxed/simple; bh=B2WSexk3yw/VKkukKcshyN9jkOKoLBIyBUeyBharWo4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SKw531c1ZwukLJQh8fuI9Qhn69zqfGK0LfzNCxC6ZjdRpp+nHbnt+I4zAxwpNiL+yhmXGaLEx3e0zdTKdx8r8PbeUh7+kMTYNQY972ws14sZRjsP6HjeO85y0QL6VjQ9s+6nMo5Sy6jNiiMsNObmkbM2nazBJ1yrZatiR2HlXAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b=bitNX6IA; arc=none smtp.client-ip=209.85.214.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b="bitNX6IA" Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-279e2554c8fso70137345ad.2 for ; Wed, 15 Oct 2025 11:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc.com; s=google; t=1760552085; x=1761156885; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vF8qB1ggi2AgO42vY2E0TYNR0wLng1Z038sHj948ols=; b=bitNX6IAAEbEmiB9Jl3g+9nRsai993y2DQ+8MfeXy9tJgDmyQvYTF8Zqb6wMQ9mShm sSum1RLa6dV+Ss8T58GVF4IHlsSmGEaORdMrBCg/6cyldPlin/IzUJc+V8+AJh49yhbG 2TBz/8Ns9LNc/65dyth35Upf9P0/cyWgD3EA8r9hAClfe3cuW1kZVwZw2/1KuMVVMEFC nKA7ragWR+cGR98g8a8uH6bhJSQnJtt0NFRB7vhEQqKc/mg4F/wdm2qsktzyl6PaFW8p almVb21sUrmJ4SwlCUI+VrOT8BNwUhKms6zVhydgjJaFEKws9SKpT/OxtVmtn+BZcilj /KQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760552085; x=1761156885; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vF8qB1ggi2AgO42vY2E0TYNR0wLng1Z038sHj948ols=; b=VXaX8wxyblvWVVLb45sUJ6hxjzcnIc4/kUVtUxrCd++Uk6dfsK7cdlvnCN29K3T1wz OWK0xxvILiAmTXQ4B9UmvyqUfG2XUuoKGJWaMfcaLetOvqdknXbilZ0pIKED8CLTy7Uu z/5zLFa6ztrmshDeRSDIePgyK8eMMj0rLRb9igT8SmAnzNyXfWdvzYIpkg0LDf4pu0g0 04H77mzM8DgGftyeqdEFWkBhhHOLweJ8JZgrS5xGlf8RkGx7tnjWV+4+7yPnbJS7yNA4 KYUIqXYTmPis9PUonpjlJQY7hgXpvtaypUrg11kbNGxGYr0877LZklzwa4GwxNf9qL9s LtKQ== X-Gm-Message-State: AOJu0YzqOEtFRL4+UwckpYG1iDrHg8MrRkprgiaknGhnoqiwWlPsHZa5 KNRbjVRk6NhLMVXn+puua/vOrBMW+bKl7Tr7w1DL/CSyjCk4MoiKBw9CZE3Wz5rzGPg= X-Gm-Gg: ASbGncuRbd81D/n5vUAs2vpZUuCpONzEtdp6kzSAVWSDEjhpdag5T/zaLAwed4HGcQV 8/7xGlsfXoZAsG2sVtfoYLu3T33JrBtMolQcDyZ9OCAdVBaG/pqbzgNdLiYehmDKquTSCPSHF37 EmdaUyuerYUHsmp7pWOgCfXMJnIQ2/Zm1yH7n+hyDeVbF5rpz7xIw+/HMjkvTiEHtA0Ao3esCJf lcr748Gpm0AOf5/ut1dMM5gnjuY9k7rAoDrU7tnlnRcxNJKpyzQGTrKbVKOLdh5nsO/fGal6ygD ra8iyY+rEtU7VNM4m1sqpQZqERyOuJGhyz3+bz8sp1Ysg0Ywf5qaAWAG4NSXIprwf1duQ5kvwE+ UI0aA3H1U66dIKVesNlq1ZS3G59Ha+SLU1Y5RKso8IlgDLx3Rhew= X-Google-Smtp-Source: AGHT+IFRxaKa/T4laOB1ws3sBGOU/x0bAxdw6xsigN7K/CZNZgfgVlPeOpzGbLKmrJG+9D7I82erMA== X-Received: by 2002:a17:903:11cf:b0:261:1521:17a8 with SMTP id d9443c01a7336-2902723b1d9mr418718815ad.16.1760552084843; Wed, 15 Oct 2025 11:14:44 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2909930a72esm3126625ad.21.2025.10.15.11.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 11:14:44 -0700 (PDT) From: Deepak Gupta Date: Wed, 15 Oct 2025 11:13:59 -0700 Subject: [PATCH v21 27/28] riscv: Documentation for shadow stack on riscv Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251015-v5_user_cfi_series-v21-27-6a07856e90e7@rivosinc.com> References: <20251015-v5_user_cfi_series-v21-0-6a07856e90e7@rivosinc.com> In-Reply-To: <20251015-v5_user_cfi_series-v21-0-6a07856e90e7@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 Adding documentation on shadow stack for user mode on riscv and kernel interfaces exposed so that user tasks can enable it. Reviewed-by: Zong Li Signed-off-by: Deepak Gupta --- Documentation/arch/riscv/index.rst | 1 + Documentation/arch/riscv/zicfiss.rst | 179 +++++++++++++++++++++++++++++++= ++++ 2 files changed, 180 insertions(+) diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/= index.rst index be7237b69682..e240eb0ceb70 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -15,6 +15,7 @@ RISC-V architecture vector cmodx zicfilp + zicfiss =20 features =20 diff --git a/Documentation/arch/riscv/zicfiss.rst b/Documentation/arch/risc= v/zicfiss.rst new file mode 100644 index 000000000000..7fb86d5ba120 --- /dev/null +++ b/Documentation/arch/riscv/zicfiss.rst @@ -0,0 +1,179 @@ +.. SPDX-License-Identifier: GPL-2.0 + +:Author: Deepak Gupta +:Date: 12 January 2024 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +Shadow stack to protect function returns on RISC-V Linux +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +This document briefly describes the interface provided to userspace by Lin= ux +to enable shadow stack for user mode applications on RISC-V + +1. Feature Overview +-------------------- + +Memory corruption issues usually result into crashes, however when in hand= s of +an adversary and if used creatively can result into a variety security iss= ues. + +One of those security issues can be code re-use attacks on program where +adversary can use corrupt return addresses present on stack and chain them +together to perform return oriented programming (ROP) and thus compromising +control flow integrity (CFI) of the program. + +Return addresses live on stack and thus in read-write memory and thus are +susceptible to corruption and which allows an adversary to reach any progr= am +counter (PC) in address space. On RISC-V ``zicfiss`` extension provides an +alternate stack termed as shadow stack on which return addresses can be sa= fely +placed in prolog of the function and retrieved in epilog. ``zicfiss`` exte= nsion +makes following changes: + +- PTE encodings for shadow stack virtual memory + An earlier reserved encoding in first stage translation i.e. + PTE.R=3D0, PTE.W=3D1, PTE.X=3D0 becomes PTE encoding for shadow stack p= ages. + +- ``sspush x1/x5`` instruction pushes (stores) ``x1/x5`` to shadow stack. + +- ``sspopchk x1/x5`` instruction pops (loads) from shadow stack and compar= es + with ``x1/x5`` and if un-equal, CPU raises ``software check exception`` = with + ``*tval =3D 3`` + +Compiler toolchain makes sure that function prologue have ``sspush x1/x5``= to +save return address on shadow stack in addition to regular stack. Similarly +function epilogs have ``ld x5, offset(x2)`` followed by ``sspopchk x5`` to +ensure that popped value from regular stack matches with popped value from +shadow stack. + +2. Shadow stack protections and linux memory manager +----------------------------------------------------- + +As mentioned earlier, shadow stacks get new page table encodings and thus = have +some special properties assigned to them and instructions that operate on = them +as below: + +- Regular stores to shadow stack memory raises access store faults. This w= ay + shadow stack memory is protected from stray inadvertent writes. + +- Regular loads to shadow stack memory are allowed. This allows stack trace + utilities or backtrace functions to read true callstack (not tampered). + +- Only shadow stack instructions can generate shadow stack load or shadow = stack + store. + +- Shadow stack load / shadow stack store on read-only memory raises AMO/st= ore + page fault. Thus both ``sspush x1/x5`` and ``sspopchk x1/x5`` will raise= AMO/ + store page fault. This simplies COW handling in kernel during fork, kern= el + can convert shadow stack pages into read-only memory (as it does for reg= ular + read-write memory) and as soon as subsequent ``sspush`` or ``sspopchk`` = in + userspace is encountered, then kernel can perform COW. + +- Shadow stack load / shadow stack store on read-write, read-write-execute + memory raises an access fault. This is a fatal condition because shadow = stack + should never be operating on read-write, read-write-execute memory. + +3. ELF and psABI +----------------- + +Toolchain sets up :c:macro:`GNU_PROPERTY_RISCV_FEATURE_1_BCFI` for property +:c:macro:`GNU_PROPERTY_RISCV_FEATURE_1_AND` in notes section of the object= file. + +4. Linux enabling +------------------ + +User space programs can have multiple shared objects loaded in its address= space +and it's a difficult task to make sure all the dependencies have been comp= iled +with support of shadow stack. Thus it's left to dynamic loader to enable +shadow stack for the program. + +5. prctl() enabling +-------------------- + +:c:macro:`PR_SET_SHADOW_STACK_STATUS` / :c:macro:`PR_GET_SHADOW_STACK_STAT= US` / +:c:macro:`PR_LOCK_SHADOW_STACK_STATUS` are three prctls added to manage sh= adow +stack enabling for tasks. prctls are arch agnostic and returns -EINVAL on = other +arches. + +* prctl(PR_SET_SHADOW_STACK_STATUS, unsigned long arg) + +If arg1 :c:macro:`PR_SHADOW_STACK_ENABLE` and if CPU supports ``zicfiss`` = then +kernel will enable shadow stack for the task. Dynamic loader can issue this +:c:macro:`prctl` once it has determined that all the objects loaded in add= ress +space have support for shadow stack. Additionally if there is a +:c:macro:`dlopen` to an object which wasn't compiled with ``zicfiss``, dyn= amic +loader can issue this prctl with arg1 set to 0 (i.e. +:c:macro:`PR_SHADOW_STACK_ENABLE` being clear) + +* prctl(PR_GET_SHADOW_STACK_STATUS, unsigned long * arg) + +Returns current status of indirect branch tracking. If enabled it'll return +:c:macro:`PR_SHADOW_STACK_ENABLE`. + +* prctl(PR_LOCK_SHADOW_STACK_STATUS, unsigned long arg) + +Locks current status of shadow stack enabling on the task. User space may = want +to run with strict security posture and wouldn't want loading of objects +without ``zicfiss`` support in it and thus would want to disallow disablin= g of +shadow stack on current task. In that case user space can use this prctl to +lock current settings. + +5. violations related to returns with shadow stack enabled +----------------------------------------------------------- + +Pertaining to shadow stack, CPU raises software check exception in followi= ng +condition: + +- On execution of ``sspopchk x1/x5``, ``x1/x5`` didn't match top of shadow + stack. If mismatch happens then cpu does ``*tval =3D 3`` and raise softw= are + check exception. + +Linux kernel will treat this as :c:macro:`SIGSEGV` with code =3D +:c:macro:`SEGV_CPERR` and follow normal course of signal delivery. + +6. Shadow stack tokens +----------------------- +Regular stores on shadow stacks are not allowed and thus can't be tampered +with via arbitrary stray writes due to bugs. However method of pivoting / +switching to shadow stack is simply writing to csr ``CSR_SSP`` and that wi= ll +change active shadow stack for the program. Instances of writes to ``CSR_S= SP`` +in the address space of the program should be mostly limited to context +switching, stack unwind, longjmp or similar mechanisms (like context switc= hing +of green threads) in languages like go, rust. This can be problematic beca= use +an attacker can use memory corruption bugs and eventually use such context +switching routines to pivot to any shadow stack. Shadow stack tokens can h= elp +mitigate this problem by making sure that: + +- When software is switching away from a shadow stack, shadow stack pointer + should be saved on shadow stack itself and call it ``shadow stack token`` + +- When software is switching to a shadow stack, it should read the + ``shadow stack token`` from shadow stack pointer and verify that + ``shadow stack token`` itself is pointer to shadow stack itself. + +- Once the token verification is done, software can perform the write to + ``CSR_SSP`` to switch shadow stack. + +Here software can be user mode task runtime itself which is managing vario= us +contexts as part of single thread. Software can be kernel as well when ker= nel +has to deliver a signal to user task and must save shadow stack pointer. K= ernel +can perform similar procedure by saving a token on user shadow stack itsel= f. +This way whenever :c:macro:`sigreturn` happens, kernel can read the token = and +verify the token and then switch to shadow stack. Using this mechanism, ke= rnel +helps user task so that any corruption issue in user task is not exploited= by +adversary by arbitrarily using :c:macro:`sigreturn`. Adversary will have to +make sure that there is a ``shadow stack token`` in addition to invoking +:c:macro:`sigreturn` + +7. Signal shadow stack +----------------------- +Following structure has been added to sigcontext for RISC-V:: + + struct __sc_riscv_cfi_state { + unsigned long ss_ptr; + }; + +As part of signal delivery, shadow stack token is saved on current shadow = stack +itself and updated pointer is saved away in :c:macro:`ss_ptr` field in +:c:macro:`__sc_riscv_cfi_state` under :c:macro:`sigcontext`. Existing shad= ow +stack allocation is used for signal delivery. During :c:macro:`sigreturn`, +kernel will obtain :c:macro:`ss_ptr` from :c:macro:`sigcontext` and verify= the +saved token on shadow stack itself and switch shadow stack. --=20 2.43.0