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Tue, 14 Oct 2025 07:54:05 -0500 Received: from DFLE212.ent.ti.com (10.64.6.70) by DFLE210.ent.ti.com (10.64.6.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 14 Oct 2025 07:54:04 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE212.ent.ti.com (10.64.6.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 14 Oct 2025 07:54:04 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59ECrhPY055621; Tue, 14 Oct 2025 07:54:01 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v3 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files Date: Tue, 14 Oct 2025 18:23:43 +0530 Message-ID: <20251014125349.3408784-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251014125349.3408784-1-s-vadapalli@ti.com> References: <20251014125349.3408784-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j721s2-mcu-wakeup.dtsi" and enable it in the board files: a) k3-am68-sk-base-board.dts b) k3-j721s2-common-proc-board.dts Signed-off-by: Siddharth Vadapalli --- v2 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.= 2392320-6-s-vadapalli@ti.com/ Changes since v2: - Rebased patch on next-20251010 - Reordered 'status' property within the node to follow the ordering specified by: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-o= f-properties-in-device-node Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 75a107456ce1..e44542b1584c 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -692,6 +692,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 9e43dcff8ef2..3740596576c0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -457,6 +457,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 837097751c18..2a7f9c519735 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.51.0