From nobody Mon Feb 9 18:21:32 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B87D93148B7; Tue, 14 Oct 2025 12:54:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760446444; cv=none; b=NixIeAnBjWD7mAxKK+4+YY4Ml9B33TfmgJIjDT6Eb1j3a8kjRYZJpq2RvSmIWwSeEfsKP2urKtoCwL2WKSMmD8vDIZ7p6SJA6nI3i0IG/h9PthCKE7G4w6vrSP2PtRSC5+SQ0Rgnv0p3WHiiyJBzBKJSD7tfUW+gIKL2ftTTYmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760446444; c=relaxed/simple; bh=zOx3QsPzNG6HraSxzi5CwLqQAMy/WKbyNlwOxgCDevM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mKiSX2158z5dS2iH8UcG2nZir/rnG0D7uy/lx1MWS3DN79Li91U4FAmHH4nC7pD0qYOzOWawQfIIV1ZmzmishZiXsPxMF1qLKWx4bHK8lZBSEA7RNFD7Wm7ZmH6yOPQjdxK62zeVZi3JkHUL9QIIzph831/j0XAlm5QaVvIg4K8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=WSOMeFM0; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WSOMeFM0" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59ECrwxY1070454; Tue, 14 Oct 2025 07:53:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1760446438; bh=Ms57JPleUvDWyECsqts6yAYPpcNevUGPOcO3spd4CSg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WSOMeFM0rhoWftgdNcLgxDBhblmAON/d4EqV1wMuvSdYr7nPi72l8f+KdaMhCy6YL nIyyRc9BvGsyTcqTuye5SAlFhQ4rG+d3nAdEYdcZ+zmt4xt+QD/77K9xwDopzdztc0 +mD+L3A/SAoHreVGI+v5SaBdOwKnGHkI6eMd3Z00= Received: from DLEE202.ent.ti.com (dlee202.ent.ti.com [157.170.170.77]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59ECrvKd030354 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Oct 2025 07:53:58 -0500 Received: from DLEE209.ent.ti.com (157.170.170.98) by DLEE202.ent.ti.com (157.170.170.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 14 Oct 2025 07:53:57 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE209.ent.ti.com (157.170.170.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 14 Oct 2025 07:53:57 -0500 Received: from toolbox.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59ECrhPW055621; Tue, 14 Oct 2025 07:53:54 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v3 3/5] arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable in board file Date: Tue, 14 Oct 2025 18:23:41 +0530 Message-ID: <20251014125349.3408784-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251014125349.3408784-1-s-vadapalli@ti.com> References: <20251014125349.3408784-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j7200-mcu-wakeup.dtsi" and enable it in the board file "k3-j7200-common-proc-board.dts". Signed-off-by: Siddharth Vadapalli --- v2 of this patch is at: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250611114336.= 2392320-4-s-vadapalli@ti.com/ Changes since v2: - Rebased patch on next-20251010 - Reordered 'status' property within the node to follow the ordering specified by: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-o= f-properties-in-device-node Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index f684ce6ad9ad..f03a15edf954 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -323,6 +323,7 @@ &wkup_gpio0 { &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status =3D "okay"; }; =20 &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 692c4745040e..fec1db8b133d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.51.0