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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2025 09:44:53.1601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1de41f-e4ab-4232-4534-08de0b06538e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7E0.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6680 Content-Type: text/plain; charset="utf-8" Add support for the 64-bit endpoint_req register introduced in CSF v4.0+ GPUs. Unlike a simple register widening, the 64-bit variant occupies the next 64 bits after the original 32-bit field, requiring version-dependent access. This change introduces helper functions to read, write, and update the endpoint_req register based on the CSF interface version, ensuring correct handling on both pre-v4.0 and v4.0+ hardware. Signed-off-by: Karunika Choo --- drivers/gpu/drm/panthor/panthor_fw.c | 43 ++++++++++++++++++++++--- drivers/gpu/drm/panthor/panthor_fw.h | 20 +++++++++++- drivers/gpu/drm/panthor/panthor_sched.c | 22 +++++++------ 3 files changed, 70 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 48bbae8931cb..c1b2fba311d8 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -318,6 +318,41 @@ panthor_fw_get_cs_iface(struct panthor_device *ptdev, = u32 csg_slot, u32 cs_slot) return &ptdev->fw->iface.streams[csg_slot][cs_slot]; } =20 +u64 panthor_fw_csg_endpoint_req_get(struct panthor_device *ptdev, u32 csg_= id) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + struct panthor_fw_csg_iface *csg_iface =3D panthor_fw_get_csg_iface(ptdev= , csg_id); + + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 0, 0)) + return csg_iface->input->endpoint_req2; + else + return csg_iface->input->endpoint_req; +} + +void panthor_fw_csg_endpoint_req_set(struct panthor_device *ptdev, u32 csg= _id, u64 value) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + struct panthor_fw_csg_iface *csg_iface =3D panthor_fw_get_csg_iface(ptdev= , csg_id); + + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 0, 0)) + csg_iface->input->endpoint_req2 =3D value; + else + csg_iface->input->endpoint_req =3D lower_32_bits(value); +} + +void panthor_fw_csg_endpoint_req_update(struct panthor_device *ptdev, u32 = csg_id, u64 value, + u64 mask) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + struct panthor_fw_csg_iface *csg_iface =3D panthor_fw_get_csg_iface(ptdev= , csg_id); + + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 0, 0)) + panthor_fw_update_reqs64(csg_iface, endpoint_req2, value, mask); + else + panthor_fw_update_reqs(csg_iface, endpoint_req, lower_32_bits(value), + lower_32_bits(mask)); +} + /** * panthor_fw_conv_timeout() - Convert a timeout into a cycle-count * @ptdev: Device. @@ -997,7 +1032,7 @@ static void panthor_fw_init_global_iface(struct pantho= r_device *ptdev) GLB_IDLE_EN | GLB_IDLE; =20 - if (panthor_fw_csf_version(ptdev) >=3D CSF_IFACE_VERSION(4, 1, 0)) + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0)) glb_iface->input->ack_irq_mask |=3D GLB_STATE_MASK; =20 panthor_fw_update_reqs(glb_iface, req, GLB_IDLE_EN, GLB_IDLE_EN); @@ -1080,7 +1115,7 @@ static bool panthor_fw_mcu_halted(struct panthor_devi= ce *ptdev) =20 halted =3D gpu_read(ptdev, MCU_STATUS) =3D=3D MCU_STATUS_HALT; =20 - if (panthor_fw_csf_version(ptdev) >=3D CSF_IFACE_VERSION(4, 1, 0)) + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0)) halted &=3D (GLB_STATE_GET(glb_iface->output->ack) =3D=3D GLB_STATE_HALT= ); =20 return halted; @@ -1090,7 +1125,7 @@ static void panthor_fw_halt_mcu(struct panthor_device= *ptdev) { struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); =20 - if (panthor_fw_csf_version(ptdev) >=3D CSF_IFACE_VERSION(4, 1, 0)) + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0)) panthor_fw_update_reqs(glb_iface, req, GLB_STATE(GLB_STATE_HALT), GLB_ST= ATE_MASK); else panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); @@ -1115,7 +1150,7 @@ static void panthor_fw_mcu_set_active(struct panthor_= device *ptdev) { struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); =20 - if (panthor_fw_csf_version(ptdev) >=3D CSF_IFACE_VERSION(4, 1, 0)) + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0)) panthor_fw_update_reqs(glb_iface, req, GLB_STATE(GLB_STATE_ACTIVE), GLB_= STATE_MASK); else panthor_fw_update_reqs(glb_iface, req, 0, GLB_HALT); diff --git a/drivers/gpu/drm/panthor/panthor_fw.h b/drivers/gpu/drm/panthor= /panthor_fw.h index a19ed48b2d0b..25ebf0d31d0d 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.h +++ b/drivers/gpu/drm/panthor/panthor_fw.h @@ -168,9 +168,10 @@ struct panthor_fw_csg_input_iface { #define CSG_EP_REQ_EXCL_COMPUTE BIT(20) #define CSG_EP_REQ_EXCL_FRAGMENT BIT(21) #define CSG_EP_REQ_PRIORITY(x) (((x) << 28) & GENMASK(31, 28)) +#define CSG_EP_REQ_PRIORITY_GET(x) (((x) & GENMASK(31, 28)) >> 28) #define CSG_EP_REQ_PRIORITY_MASK GENMASK(31, 28) u32 endpoint_req; - u32 reserved2[2]; + u64 endpoint_req2; u64 suspend_buf; u64 protm_suspend_buf; u32 config; @@ -464,6 +465,16 @@ struct panthor_fw_global_iface { spin_unlock(&(__iface)->lock); \ } while (0) =20 +#define panthor_fw_update_reqs64(__iface, __in_reg, __val, __mask) \ + do { \ + u64 __cur_val, __new_val; \ + spin_lock(&(__iface)->lock); \ + __cur_val =3D READ_ONCE((__iface)->input->__in_reg); \ + __new_val =3D (__cur_val & ~(__mask)) | ((__val) & (__mask)); \ + WRITE_ONCE((__iface)->input->__in_reg, __new_val); \ + spin_unlock(&(__iface)->lock); \ + } while (0) + struct panthor_fw_global_iface * panthor_fw_get_glb_iface(struct panthor_device *ptdev); =20 @@ -473,6 +484,13 @@ panthor_fw_get_csg_iface(struct panthor_device *ptdev,= u32 csg_slot); struct panthor_fw_cs_iface * panthor_fw_get_cs_iface(struct panthor_device *ptdev, u32 csg_slot, u32 cs= _slot); =20 +u64 panthor_fw_csg_endpoint_req_get(struct panthor_device *ptdev, u32 csg_= id); + +void panthor_fw_csg_endpoint_req_set(struct panthor_device *ptdev, u32 csg= _id, u64 value); + +void panthor_fw_csg_endpoint_req_update(struct panthor_device *ptdev, u32 = csg_id, u64 value, + u64 mask); + int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_id, u32= req_mask, u32 *acked, u32 timeout_ms); =20 diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/pant= hor/panthor_sched.c index 0cc9055f4ee5..25663de62b8e 100644 --- a/drivers/gpu/drm/panthor/panthor_sched.c +++ b/drivers/gpu/drm/panthor/panthor_sched.c @@ -1138,12 +1138,11 @@ static void csg_slot_sync_priority_locked(struct panthor_device *ptdev, u32 csg_id) { struct panthor_csg_slot *csg_slot =3D &ptdev->scheduler->csg_slots[csg_id= ]; - struct panthor_fw_csg_iface *csg_iface; =20 lockdep_assert_held(&ptdev->scheduler->lock); =20 - csg_iface =3D panthor_fw_get_csg_iface(ptdev, csg_id); - csg_slot->priority =3D (csg_iface->input->endpoint_req & CSG_EP_REQ_PRIOR= ITY_MASK) >> 28; + csg_slot->priority =3D + CSG_EP_REQ_PRIORITY_GET(panthor_fw_csg_endpoint_req_get(ptdev, csg_id)); } =20 /** @@ -1303,6 +1302,7 @@ csg_slot_prog_locked(struct panthor_device *ptdev, u3= 2 csg_id, u32 priority) struct panthor_csg_slot *csg_slot; struct panthor_group *group; u32 queue_mask =3D 0, i; + u32 endpoint_req =3D 0; =20 lockdep_assert_held(&ptdev->scheduler->lock); =20 @@ -1329,10 +1329,12 @@ csg_slot_prog_locked(struct panthor_device *ptdev, = u32 csg_id, u32 priority) csg_iface->input->allow_compute =3D group->compute_core_mask; csg_iface->input->allow_fragment =3D group->fragment_core_mask; csg_iface->input->allow_other =3D group->tiler_core_mask; - csg_iface->input->endpoint_req =3D CSG_EP_REQ_COMPUTE(group->max_compute_= cores) | - CSG_EP_REQ_FRAGMENT(group->max_fragment_cores) | - CSG_EP_REQ_TILER(group->max_tiler_cores) | - CSG_EP_REQ_PRIORITY(priority); + endpoint_req =3D CSG_EP_REQ_COMPUTE(group->max_compute_cores) | + CSG_EP_REQ_FRAGMENT(group->max_fragment_cores) | + CSG_EP_REQ_TILER(group->max_tiler_cores) | + CSG_EP_REQ_PRIORITY(priority); + panthor_fw_csg_endpoint_req_set(ptdev, csg_id, endpoint_req); + csg_iface->input->config =3D panthor_vm_as(group->vm); =20 if (group->suspend_buf) @@ -2230,9 +2232,9 @@ tick_ctx_apply(struct panthor_scheduler *sched, struc= t panthor_sched_tick_ctx *c continue; } =20 - panthor_fw_update_reqs(csg_iface, endpoint_req, - CSG_EP_REQ_PRIORITY(new_csg_prio), - CSG_EP_REQ_PRIORITY_MASK); + panthor_fw_csg_endpoint_req_update(ptdev, csg_id, + CSG_EP_REQ_PRIORITY(new_csg_prio), + CSG_EP_REQ_PRIORITY_MASK); csgs_upd_ctx_queue_reqs(ptdev, &upd_ctx, csg_id, csg_iface->output->ack ^ CSG_ENDPOINT_CONFIG, CSG_ENDPOINT_CONFIG); --=20 2.49.0