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Tue, 14 Oct 2025 01:57:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CC.mail.protection.outlook.com (10.167.240.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9228.7 via Frontend Transport; Tue, 14 Oct 2025 01:57:12 +0000 Received: from localhost.localdomain (unknown [172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 5A5AD41C016B; Tue, 14 Oct 2025 09:57:12 +0800 (CST) From: Gary Yang To: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH v3 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Date: Tue, 14 Oct 2025 09:57:10 +0800 Message-ID: <20251014015712.2922237-2-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251014015712.2922237-1-gary.yang@cixtech.com> References: <20251014015712.2922237-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|SEYPR06MB6278:EE_ X-MS-Office365-Filtering-Correlation-Id: 9eb54d46-e60b-4c9e-1a65-08de0ac4fe6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2025 01:57:12.9677 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eb54d46-e60b-4c9e-1a65-08de0ac4fe6a X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB6278 Content-Type: text/plain; charset="utf-8" The pin-controller is used to control the Soc pins. There are two pin-controllers on Cix Sky1 platform. One is used under S0 state, the other is used under S0 and S5 state. Signed-off-by: Gary Yang --- .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinc= trl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 000000000000..6c83eb47f974 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Pin Controller + +maintainers: + - Gary Yang + +description: + The pin-controller is used to control Soc pins. There are two pin-contro= llers + on Cix Sky1 platform. one is used under S0 state, the other one is used = under + S0 and S5 state. + +properties: + compatible: + enum: + - cix,sky1-iomuxc + - cix,sky1-iomuxc-s5 + + reg: + items: + - description: gpio base + +required: + - compatible + - reg + +# Client device subnode's properties +patternProperties: + 'pins$': + type: object + additionalProperties: false + patternProperties: + '(^pins|pins?$)': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing= the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, and drive strength. + + properties: + pinmux: + description: + Values are constructed from pin number and mux setting and a= re + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h = directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + description: + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15. + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h. + + required: + - pinmux + +additionalProperties: false + +examples: + # Pinmux controller node + - | + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) + #define DS_LEVEL4 (4) + iomuxc: pinctrl@4170000 { + compatible =3D "cix,sky1-iomuxc"; + reg =3D <0x4170000 0x1000>; + + wifi_vbat_gpio: wifi-vbat-gpio-pins { + pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D ; + }; + }; + }; --=20 2.49.0