From nobody Fri Dec 19 20:32:32 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25D572F5A13 for ; Tue, 14 Oct 2025 10:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436179; cv=none; b=hH053QAJPh2ddur2dcwDUpiL0lBvgE6cLixjJOvvHs4n0NQV3n82jgQ7/mP/ECY81NAYWEVn4RAz+GWdNtSPummFw3g0b99JlGNj9mmKCOKXz8nD6gFi+TZAATYOkIdnGxB2HGspTuIIsLGU2Cuem5vJbMqgUvrt+OAM6W1Qrjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436179; c=relaxed/simple; bh=SjQNMcKFiFxf1UzqcFbV5V5FIrz1nf5P1xbHJ87t43c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XFC476muCmzwVyKL00MJfpkWfm7KqDYhzTroiQZVnD131Us3WSBa1vQrTHeHwvEbnZNW8OGHXF5U8nHUKD67ZhJV1ygCLu7Qntg/SFcVR+MJf5aX4CxlxHT/axIM14l87NO0dNtCQCq5RF0grpR8q/DhpWIIr6sBR8YW5e4XmgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rg+Vx0Oy; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rg+Vx0Oy" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-46e6a6a5e42so22427965e9.0 for ; Tue, 14 Oct 2025 03:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760436175; x=1761040975; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cVJfqn+CURZR5kgzfDjtV++23e8mA5V4+ieWpLbcMzI=; b=rg+Vx0OyC0tKcb+PkXiZfGOl3Wxsg+Ht/I4kztmIH7KvASEMHNz7KHbBTf76rS4r5U b+3sgrQta9u/XoKTRefaOncJ1aLQ+I4l6Hctxf1w1NQB8ZNpygG1hOlzzNFJQs0iCbK8 KR/7ce3g7xI9c7PhUMs8SXVWyccNRtNvKVtyfiks5F9ahCzxr5H6p3aUhFHzWllWkdCK RyZho6Wui23kftLL7Jp9cn8V7uPtQYUFt+ID3r8fZ66wsUG+t3slaibv735VkD/A//kN xgFe7e6dLO5z1SCoobg554dOHN9MXVWr5U4AwZ48hsfogNg+tTdaDCBd+Fnh674jEAVt DHyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760436175; x=1761040975; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cVJfqn+CURZR5kgzfDjtV++23e8mA5V4+ieWpLbcMzI=; b=N36m7nNUsBsTXE7rlZesSKydBD0dHDijco7fnlMrAzpd088l/AOlPvS4hRQ3JPNHwT ydBu4vjTGqSPJFfefGCzanqaCOLOXHcPRgKG+AgxMw8r/CmJjrWvNlLUrbXnUcXipQeF 52elJkmcxxb6YBlY/KbGoLSyT4PEWzH2MS1P0hLRDPDxZkeB3b63F3Q5gnjOnpCs6wW8 60CwoppSP8QETMt3cV5i5KSRKaMYgc1gVjvgYvFumotabU/ZAN/TdQhl4azO8Ukb0Vae MMW78Au0lyGJ0ew+cWovakSNsi0HJDw4cuDiy22NfZ0pRdEoyWW3dLMGaHxCOZuhCjVd xP3g== X-Forwarded-Encrypted: i=1; AJvYcCXNfKV0XrGnkhsmlijt5kWLZWPpc5rOPz3zDm2Bgd/FMIrVcD41OPI5MDauMPKm8VI5oXonCd5Dzd6dIqI=@vger.kernel.org X-Gm-Message-State: AOJu0YxXLtMskKdkR3GNdbt54u5KnXOfabSzJ2V+GM5ryiwgqrq48wH0 BG4LzLJLmwmOK+FsjbqWAN0SpQ48NqnwWuzmg/q0fvtOl3dN1+CZDh3fPuljsI+zF2g= X-Gm-Gg: ASbGncuOoxh2A3LJMz/nOSazo48G+tRGt2v9zbhhRbvnV3F0j9aRbjS5H2yfj+qmnbl 92z7xl65cMUYdtw15bai+nES7DXL/lyGInDcqCTyyLVyUNtj0rfgUJSaENCX5NerLfL9ZB1mc9J SNcDXl+VIMc8AGgSUR1+fnKTka56/r0XHJHA9RmO0KLOikC58jk4VzaMsB/DdUD5g1tPfNAb5Bc rfwedQ3eV9s6GWFxvC6edgN2BHwM9Ygg/neN/zOzUoF7+rH5L/VMUdkAfdQ0sYPUugYZQ7xRCKh oxHHL6rZGhc8Yjng8THDYxe2rPktHwNDDoAiedES21YkUhwfNVsSSQWMn0ZRg+0NsJNCL9k9toP 2sSQHNVKjYisZ4d/jCYxVDb7Uad353VUfCgVkP+uibDw= X-Google-Smtp-Source: AGHT+IHn1J3P6w0TT3kflXZRWIHbxv02CVqgaJ7Zj1UOEcse11mXhprORjqLY8jjisVskI0JowAdcg== X-Received: by 2002:a05:600c:1e86:b0:46e:4581:6634 with SMTP id 5b1f17b1804b1-46fa9b018e1mr176937295e9.29.1760436175311; Tue, 14 Oct 2025 03:02:55 -0700 (PDT) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb489197dsm239615305e9.10.2025.10.14.03.02.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 03:02:53 -0700 (PDT) From: Abel Vesa Date: Tue, 14 Oct 2025 13:02:27 +0300 Subject: [PATCH v3 1/4] dt-bindings: phy: Add DP PHY compatible for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-phy-qcom-edp-add-glymur-support-v3-1-2772837032ef@linaro.org> References: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> In-Reply-To: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1167; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=SjQNMcKFiFxf1UzqcFbV5V5FIrz1nf5P1xbHJ87t43c=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBo7h+/P9kfefQL9Xhu238N4OW/+ki3a8ZQcLA+5 /LnZTJxNsaJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaO4fvwAKCRAbX0TJAJUV Vg0BD/0TH9WNgHrWjeqkeEuXihRVj7jKEy9+iMDKrSQ8/rwR7ChvS6cRGpe+u/O4DAzGomvgO8Q lx7b2fwpoWlEowETy6PImWEB2TmpNXUBdD4zo/BDHLaoISEcdcHToJpihgWYI5rMnQ9zhRIKshe q9ufkvxu3L/+/u+FG9LCc7sES2xB8WjJFaoPQpROLNfaNB+9455YfeteCb3SvePUAzbtO3qJavG P4igEdfz7GaknEHv9wlIiYb08v5jJJKCc+PROmlHQfojvQvbED6Rn9+YuymS57MnV0bhTRt8Mb9 QVXW6+6YpfLU3eTjLBgPlrGF4wjF0kuAl766P+FjYwDscU0MUaTXk3FVehoO2uLB3KXmXJpvpQT zTlh2jLKjy/lJk9aHxChoS/hVQk3Ac+U6LPqYcfEplRrKF9nXeBWYoRbQ4+olOltcY01+QnIeKx 1Pp/9Wx2UxS4HDM3pFw8g3MvCkA8FRpo5kcQXqDBFVt1+kFy0vUhmlD3SIzpzohIgWX4m1+tx3X WsPCgPkRq9UoKN9VSpzP1urz1ueT52u2OrGpa1X0AbIvOCaE+eBdacV669Tgx/F1mk6nR5OynX7 lar0vq/2GI9bGPxHKSu0ZAvctRDk2YWF6csnxydqF1krfDNbM0Gh7dxwEVGM05IFMnpuhpkrJLX dxT0tKQyUxjylrQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Glymur platform is the first one to use the eDP PHY version 8. This makes it incompatible with any of the earlier platforms and therefore requires a dedicated compatible. So document it. Acked-by: Rob Herring (Arm) Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index bfc4d75f50ff9e31981fe602478f28320545e52b..4a1daae3d8d47ca5f08d97a1864= cfd615dcf108d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - qcom,glymur-dp-phy - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy @@ -72,6 +73,7 @@ allOf: properties: compatible: enum: + - qcom,glymur-dp-phy - qcom,x1e80100-dp-phy then: properties: --=20 2.48.1 From nobody Fri Dec 19 20:32:32 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AE872FE049 for ; Tue, 14 Oct 2025 10:02:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436181; cv=none; b=hIIBhwsQXO3nvx7Kam37wA4eWjhKQgB4ZiWnvwgQ9Xpab7WVM4Gun0/ZUixVRecJmrlxyKxnLshqKo1vCtccD5AATNn2zPUcVtmhxmIB0Z8fv09TCcyfZ+9IXRTxtTFVsdeHPofOiKtpPbc7g1mMmuihbup2WTBfCOdosafGzN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436181; c=relaxed/simple; bh=S/KD30P8NP0mNcehUP8pNGC81/R9glKXIgh5wrx2AKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IpaCbhZxPdY/EQr3sGM/iAXaD5HCIkIj3RMPEYNhLk4BeieGe+DyYlIXsLugygEo/K2wuyTPtJ4MjZEi2pKG5IKBYYpc1n1oO+C13UtdNIyoTfyAdKxxTLMM9EClHZ0i1EwUWq/uxe6V+5s0aZh1s8QhDl2fbekrBa0usWcO9ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Yxdma8ai; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Yxdma8ai" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-46b303f755aso44617335e9.1 for ; Tue, 14 Oct 2025 03:02:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760436177; x=1761040977; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vaS07fRAp2KaqILcMQz5dgQ+s6oWbriezT3s15GrHVk=; b=Yxdma8aiLQ93OFxDCuGOp+G+5fdfAdevdgwyJbx/MFxCZSkSSHpb3S5XJECnvak8qe FPQ/YoSNalIXS4P12iAeOtwF6JP11r4LC+4L9qLmZqcBmPfL0lPbB8NBxvO8t44hO4/a N4xJj/xJNUHX9Juk7+WB1Xg2hGxt9n3GYlZzJSchReup72sICnV8BFtnpbus6b+Cv8OM UqlebTnScMmcpXZz5GsMnnljWzK0sh1tCm5aX7NTAbUr2hxvRBj3xpOuTG5RmjHSZ4EJ vjt9YrtBYoAjYUDrKnIN4bMyDqKTABZi6jNELqpOM0jVPHPoX8hw9unbo+VveUTSoxGE tpmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760436177; x=1761040977; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vaS07fRAp2KaqILcMQz5dgQ+s6oWbriezT3s15GrHVk=; b=cz8sH2XrFOqvgXGRQ05+z+x9tG50KJftG/qwlrHpS1pbktV4oB8s6SBQ/SNouB8R46 ILKrHDGpOu7ooTR+iSusgXyG6H68c904q4jMB/+DCv4w/MsILgGXh4I814iCM8MRnqQG 7Ip06RN3zg/9c2QKMSsOTq9jf2ijHy3WW73k5y28oOKSWmJ7DmT1uDeHmU6SAi+ITOr7 Mwjkc07nZE4pW6na9wzWEPc8S/3KYeKFXrLF75lE2F0cPmDoMqk4qLYg3Ie13GWu8jSY W1zf2rifgPvMlwONGuPw/0RPxBORnDNbfowXttO3qBZILvu4q/VKfa7xOH5VmhfPrm7x QDAA== X-Forwarded-Encrypted: i=1; AJvYcCW9j272hShBqGMv8bplJUFsgEjoEkw+55ds4q4YRjV4V52n4zJ9PtUXBACrjCXXrBLhrEzvsILF6DXquSk=@vger.kernel.org X-Gm-Message-State: AOJu0YzkvljzG27JVwDAm2UoAVOf6R1dUGG97hAFQw8LW0FGa1fLa4vx FBmPQeVQhr6JGci870g82tBWHvsps0zTJS6wd43JdqnrhGm0q38h1cAl7OrvjOexH6E= X-Gm-Gg: ASbGnctbDewUW45EpyOkQKTa51vVBEPJrMI+14BwnogHPCOW4oTaRzYAVv0UH0CHl5a O1mQViqPJ24Q26zvgT8t6G3TAkrCCDfFybCJA0HIShQZ8yi+Tm5qKiC/zwng16qirWl1IuSDIsH cRJag3Cea32CuhCq8kpaCAWDpYVxFjZE7XWBmqVlvEIqiloFxoULcuoVcf0UpefAaFx0kvOgugW a9Kk0BM8RC7EP908WyDNmZqH6r+pZYmLAXu2la8bhSRHcbEFxEPNeDrIqhwPCz+qJJQJh2IDZMO 4QmDmx/w+7Y4BvlRZg6jiT2IyBlI1Ui28flSZHRelRvMbZzwdd3qn2NK8VKTDXi++eKSgdph/Bw LN2E97Hfo8x/yg/3uW2fq8BaSPEVgKKIn0FuglA+GGlIPbiOP2HxzDQ== X-Google-Smtp-Source: AGHT+IFl2VtEUnOc7K7cnKyCXWZQmxxjgC+HM/RYs8PRHoUIntYpayCUFq/QGa3L5ZN0P6heHafASA== X-Received: by 2002:a05:600c:1d1a:b0:46e:4a78:dea9 with SMTP id 5b1f17b1804b1-46fa9af17d4mr168450155e9.17.1760436177412; Tue, 14 Oct 2025 03:02:57 -0700 (PDT) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb489197dsm239615305e9.10.2025.10.14.03.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 03:02:56 -0700 (PDT) From: Abel Vesa Date: Tue, 14 Oct 2025 13:02:28 +0300 Subject: [PATCH v3 2/4] phy: qcom: edp: Fix the DP_PHY_AUX_CFG registers count Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-phy-qcom-edp-add-glymur-support-v3-2-2772837032ef@linaro.org> References: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> In-Reply-To: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Konrad Dybcio X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1247; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=S/KD30P8NP0mNcehUP8pNGC81/R9glKXIgh5wrx2AKc=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBo7h/Chm3XpAOoZ+7P1ptsAjAqkDalQY4X3MdGn QpOsnA+z8iJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaO4fwgAKCRAbX0TJAJUV Vt/EEADIKuOmzt2Kab1SDBpuRUMisq3zDdHGoozaSKWUjDdjzmyUsli4WK+J726o7f+wz/nl35c p/kuytzWM6WmVhNy2uKr3bTBevx3TTZ/khpJOTvjXJD88U0nkiJKFKSw7OtjbRDsPfHNVMRckEI XmOO5XxbfoXMDIA9zzEL85yyhcVCvSwMxm4Jl90kloBBBIQxQbfQoeSQtvSVtGxSAE6LW30lW3+ K59yh/TgbMvl6RCnVS6DJPdiHMvJAk0Zt3fW73KrH1m34+c06n0M0495ABtxd9noT7yP5milXcb GP6dGequX+u4P/yA3tM9vyd6GgTPHb3TBnQQ7bDQkIPyEe1F4o/vcW9q2q4G1bmFVNKKw+pnvqp DSOPcGQ9W/P8RpEoBDU7b4hrVm4LjeNT2IQvjjH8OVXQPzaMDJ3zvAWvYJsJbiXLSak1LyfIXxi ryttjR+DDMutxAj5gh/8PLigLof3N8WYn5Caauk361g5UyeS1y1xRkL9QQyeB+/TrRPuXnqy5DH 6O1uIIO6JmbCQEqTMEaZ7lSouhkkmKaS5QFZQgo8rT7UqNQGenxFOkqEUc5tvnDup5hsF3YGDoM DWtAWrgFO65A/6Guiq6jnkc+Y5YXtji5LchjQCmvHYyCQXiCTCL+11Q+GG6JEJeiTg5ITXHTkSb sYesTJCzcqS3h9A== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE On all platforms supported by this driver, there are 13 DP_PHY_AUX_CFGx registers. This hasn't been an issue so far on currently supported platforms, because the init sequence never spanned beyond DP_PHY_AUX_CFG9. However, on the new upcoming Glymur platform, these are updated along with the rest of the init sequence. So update the size of the array holding the config to 13. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..7b642742412e63149442e4befeb= 095307ec38173 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -32,7 +32,7 @@ #define DP_PHY_PD_CTL 0x001c #define DP_PHY_MODE 0x0020 =20 -#define DP_AUX_CFG_SIZE 10 +#define DP_AUX_CFG_SIZE 13 #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) =20 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 --=20 2.48.1 From nobody Fri Dec 19 20:32:32 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD18307ADD for ; Tue, 14 Oct 2025 10:03:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436184; cv=none; b=rEzpzj+mh2+qftABH8mIMIdOFJHfE4piXb0mmZPwxiqAAlIIfqvzot4VD805l90tLZ2hRk1ihmHjWsIPf7u6NVGPhM0St1k0WOws3JA03Ubdo0KvyfjJiWNvsU3mW0RZYJjBkJGT0ppiphhx1ODBpw+Rc/Nj6t6Ok7ihqkt3q3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436184; c=relaxed/simple; bh=BgmhdRMvLlgpN/7k6aQQi92mlj64RE1e5APUgFOVVyc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SEXHEts6TQNwoDpgdV2F/NqvvLGVKxW1NWZMKMYjauXLq9+u10daGMQFXPt9LBHr6mDtP7PlOt5Q7/mB0ErLYL1+24XZEChAzxjpkN1jroSD1rX2PrRulkmqb+Xd+Oq3WQCA0nlOmRZhDidyu7hS6I0NRVqxYuoau90eA/AEpTM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=za/2JYZS; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="za/2JYZS" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-46e2826d5c6so30723695e9.1 for ; Tue, 14 Oct 2025 03:03:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760436180; x=1761040980; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oe1S5QdAgZ6PQC+SmWz8IK3Ii5YFBwtBoAcJ3b2LeJA=; b=za/2JYZStWMhJPkXWw98xPwtr08XUJW9sZu3l1M2a1YOyqbBjfWlHu3URFjrKeu29T mnHqezEoGElKGw1Pvjz1VaSL4rSfdgPifBQWqBpofJc2DAKWFEOu9PaNjOt/q6+72lOY R5lrzQa2lMPH/h1Lj96fgBC73xiw+QuVYjh49KrcCY+1JM7sYG+HzEmX8YZJbmf8F1P7 5ZJ9BgUOgj1hIfP1GCsPsmIneDX8mA/+NMV+BzYUb7R0V8SrKiqkkWj7jOGMGiLRDbdY 3b2pukweA9LEMpwXRosGPQqO9iT4xxLAXJ0PX0n1M8GnhTcpsCdv59tZOiZLYFEnBKxq fJYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760436180; x=1761040980; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oe1S5QdAgZ6PQC+SmWz8IK3Ii5YFBwtBoAcJ3b2LeJA=; b=dSQfZlrkL8r6kvULkjHrL7Hi/wzN6u20yyqEHCEOrmORqv6bfP7QAprgBdbsON9SQu L9TGedsHn4z03TiYhKFsb2KDySLERbFsdk51t4htLXIgH8ufi5Zg5zPWZw1ratMwdSA5 gpD9reyE/pYBT0M1ziZZOAkiMvrkiqQUFSJUaYqihMTmOOGM1NwtMJqFE39wAA7/xyk1 ArXJR2fEcPZCh8uhY+/uE5xMys390fMPvyqvKqyUw1TdTo05/Z14f+3K3o4CHYjZMIiy KthO/0nL0HaJF9wRHh2TdSSgdKA++SBQyeqXyrnyooqaPGImtMp7X15xYi5wapmw5/Ge W/0A== X-Forwarded-Encrypted: i=1; AJvYcCXIdRdHPXKBpEjlM+YrWKyp9lZjjffKKzDATR01An7bA4a6FrVJtQZyeENjV7X4TkRSM9yskXyKS4N7W1o=@vger.kernel.org X-Gm-Message-State: AOJu0YzqiDc0eT8jPHIh9o+0jNx1i8Vt0YvOig8QHc2ByKGSopvLx2E3 7g+mChM8utxOsdqb2T6/gV3i5/q4ZLUR182xXLf7XmIGIAui5KScf5IHEQz57QoFLnM= X-Gm-Gg: ASbGncuKYxuYFN2fEKYBh6sf5TCl8YKuGDcAu9uBuI0ZyXiPDOOWJ1wL+0/4iGppplp 6OmJ//vcJrhwJlVu52fUs2/cSBwlKLTfzEcR/rsmpisaJz5rfY04HTDNvIjHRSl+sHkUqhzmaWk uMCwYx1TtTl48b48rYSv74qCzPKWcHG7pXgfcGEPsqWhsdvNtvaVjtv2DKf1yWt0qjCBUVQOY8y 5T4com1L38DciiNHWwVpTCXx2emWWkLI4Mg7QC5rFqCzQ53zak+bPFerPtbKfCcOjA3An/5Ixjn 1ULZpVksPFWIx1TI7V0PTxZA/TWaV4TE47crskDh0WrU2wtKB2+Vthpgdk99k9fwDBnsb0Eb4kZ aNbJNkELSiXUi8Wu1d6z/5qcaeXEVflkkuJNcKrtwzvcnZSTqxIXnIdYrcYYewzMZ X-Google-Smtp-Source: AGHT+IFXQlAiZxUpsOyWjLYxCb+pvuSYy9txnYsOvvpPOnU09dHCFC7P0rFzgIwqYP2wrZy+bzd05Q== X-Received: by 2002:a05:600c:4586:b0:46e:4883:27d with SMTP id 5b1f17b1804b1-46fa9b079a9mr175260475e9.30.1760436179564; Tue, 14 Oct 2025 03:02:59 -0700 (PDT) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb489197dsm239615305e9.10.2025.10.14.03.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 03:02:58 -0700 (PDT) From: Abel Vesa Date: Tue, 14 Oct 2025 13:02:29 +0300 Subject: [PATCH v3 3/4] phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-phy-qcom-edp-add-glymur-support-v3-3-2772837032ef@linaro.org> References: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> In-Reply-To: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Dmitry Baryshkov X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=3130; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=BgmhdRMvLlgpN/7k6aQQi92mlj64RE1e5APUgFOVVyc=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBo7h/GA0vAQpCOUSzu7GQbh+2HdAfu23u1UpDub WitMODqp7GJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaO4fxgAKCRAbX0TJAJUV VuN/D/9IfUrD89o1znhS/+WIZEUUX22u6tBBNtCfgoIn1xFZwEHQGZ4Y8rqqdj5oxvsUHw77llw iLVkZz30oOmeWU/L6ekYL5QKZtfaCLkj759plcykOir9hdj8ZorRWgqgYqk/wNNAeOGBJDjKoj3 7b/bkrCnH6oxnKT/QSaBUT6BJXImE9hGNOau77blIPM9fxOaHMCJ0GuHZnqW49IWE0mQ71yKrCy ZrDu6nIdS5jAC8VfrjVITCHCSfEEyP/WqRhLHcuHxYB7fe38z2QO5F6SrQDdKFnaVF6dsqJT+p1 dyzeuwZdM6VqZ/P51IatZdyGP0JN6sewENPGo183lagBs2GXx8jABFeqOhNNR2D1yZ3rcVFr+Fz MwcM/b+spsB2IfyhmyPbw7+Gl4ZlYjTDfFSjvPmMjY/kEGn/gachZbBqBispFHTRbXURxIsgp/5 9ni3B1lhmd9BRj6kveErpT56wODedqJJUisCkXLkxgNW2mnvY874EjPFw8cpBu0DpxDfIk6qVNI X0I6tyyHO5wVPCCxb7M2JMtE+8X67oOUYSUZVPzPWSSCBew4r4OYcefC66fzwlAhCLUvRVR3msX /s9ys6tIFBvw4HhZsRBbmNvCy69iFvpYGCww6VynwmA6iOt0Frn1jXJ1sDJ+VHBJcDhkY2Zt/gg qaglYmirNyQHdPQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ for the same version number. So in order to be able to differentiate between them, add these ones with DP prefix. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- .../phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h b/driver= s/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h new file mode 100644 index 0000000000000000000000000000000000000000..2bef1eecdc56a75e954ebdbcd16= 8ab7306be1302 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Linaro Ltd. + */ + +#ifndef QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ +#define QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ + +/* Only for DP QMP V8 PHY - QSERDES COM registers */ +#define DP_QSERDES_V8_COM_HSCLK_SEL_1 0x03c +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 +#define DP_QSERDES_V8_COM_CP_CTRL_MODE0 0x070 +#define DP_QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 +#define DP_QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 +#define DP_QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c +#define DP_QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 +#define DP_QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 +#define DP_QSERDES_V8_COM_DEC_START_MODE0 0x088 +#define DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 +#define DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 +#define DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 +#define DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 +#define DP_QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac +#define DP_QSERDES_V8_COM_BG_TIMER 0x0bc +#define DP_QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 +#define DP_QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 +#define DP_QSERDES_V8_COM_SSC_PER1 0x0cc +#define DP_QSERDES_V8_COM_SSC_PER2 0x0d0 +#define DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc +#define DP_QSERDES_V8_COM_CLK_ENABLE1 0x0e0 +#define DP_QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 +#define DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 +#define DP_QSERDES_V8_COM_PLL_IVCO 0x0f4 +#define DP_QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 +#define DP_QSERDES_V8_COM_RESETSM_CNTRL 0x118 +#define DP_QSERDES_V8_COM_LOCK_CMP_EN 0x120 +#define DP_QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c +#define DP_QSERDES_V8_COM_VCO_TUNE_MAP 0x140 +#define DP_QSERDES_V8_COM_CLK_SELECT 0x164 +#define DP_QSERDES_V8_COM_CORE_CLK_EN 0x170 +#define DP_QSERDES_V8_COM_CMN_CONFIG_1 0x174 +#define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL 0x180 +#define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 +#define DP_QSERDES_V8_COM_CMN_STATUS 0x314 +#define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c + +#endif --=20 2.48.1 From nobody Fri Dec 19 20:32:32 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C61D3090C7 for ; Tue, 14 Oct 2025 10:03:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436187; cv=none; b=GosWcFtsZRBZ/B4NEwKQ7nBhVFAtVw9FW+wIZVFhXbmN9eQLZlqEp19hHFAudTTm1BGUcRflFAIKsbDEl4H0MrdzgR+Q2aOzcbFIh6ZyiGGEG19wfBZmuY7Mhd0FLH4CwzMYOODNKNQglFVbwmGM5mO5mm97QVrf1MkniZDXirI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760436187; c=relaxed/simple; bh=YCJPvHG7Gmp3ymjunk6DqHGq3+Tdfwwne9NOLTKD9es=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SSG7/ZCrmLhjWRZdMDUKszl9CNo7DLxgYwxFqYmyKyV53V/o3tQyy2t9No5vuRz/IR+0QHrEhQhUgwdVn1dB02SrIpirwGVOQyLBmME+7GP37pUoZCPW3AA2jO8QBDM0HmlUKDBRVW1085wi9/0iiEB17feeJF8kNp5NVsAuWNE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nbT7KLmd; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nbT7KLmd" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-46e3cdc1a6aso38456245e9.1 for ; Tue, 14 Oct 2025 03:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760436182; x=1761040982; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MV02rGTUDlT1ggqlYQ8IxMHF6US9L5gi+se7+XP/fhQ=; b=nbT7KLmdtWtNkNGjYzL6qtessFjt9uBmLJ1Q051FkmbyOfsxjgbF3kuNImEH7g7Tg2 0uO4tlOaxFbJRQDPJpxfme2VHGGIlT+1ygBrl4P5SbslTXnDT+uDgDH81az/KsEmeypx jihG6XQt6ELMz4UrdVne3TTODYnnXLux3S7JiItl/K14wfnrxZaNlj5EQY4vzqI8Nnoz 1qPJ/mlNnA1SPioiLjfYXvFq+aPBTU+OrffoY78CB8+QsO3Kfbq/M4GffGtDgnlvH4rC poJrd4WnIJFvhzvQ9Zwp9UmwJBw592jbdRyhK0CyZq3ychLMwyECCkeLM6cWWnzc8nas dp1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760436182; x=1761040982; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MV02rGTUDlT1ggqlYQ8IxMHF6US9L5gi+se7+XP/fhQ=; b=Bh47MdSY+FxWnOQCCbL9OcfCc5kbs1NIp2y8f4ALvw84hX+wRYYhP2hag+5zdareNG 6lAuUQmK/6sfL2E0QUOGY7+/mhuyk2Nd+WzEGnsp8FNUl9SXnz0DhCJWzUKtFOcC+mR+ Wq3hw6eivtupcfUOredYCC4gzQhmu0y4qj+GKyuGAitQgzMqCu9lc1uQUNVWfjOP++YH fmRm0WYhMA1dZqzUkdBwrX/nZFxfoC93Ach7ZTF9Sj6lPI2dKE343/DjSg5hh0AHBZGU dfg/z9M8EkNhWtaIkmvTweiNv4KL3S/0QfkaLAqnL6zJ+ztZx4OCfPtZhzuFsc4oUZ+T MmvQ== X-Forwarded-Encrypted: i=1; AJvYcCWk9RLCFaSgazTnHhOWm+FWHIwMxpa54OvEaKyIX4XPbs0w4f/N8a7Rwnmiyo45K+TgFP9LSVgzf4+mAMU=@vger.kernel.org X-Gm-Message-State: AOJu0Yxo7LWXm6A1hJCPIbBfVuPdLI6+ktt2NjHt19XZ9yCzgKnc4m/1 mABa6kDmZ8QjNqxDuXP53DW8zWD163mradNIuCkh+m8c31Q1W31WOjmhvjMjB7xWBlw= X-Gm-Gg: ASbGncvwI3ZdaiqgTV2QZahoJm4bp9ylcUESzcYB8qe1776zmkVD2DM7rqAH5QxVR6w LTYYvVYCvVMeHY9tiq9k+8x/Ra8CoS6xA/nWqBYaze48WzAJdNhyULAca/t/amI+KWpkMb6uGJh 1fjMAdXcWBAT23Lx96YROUU08ycAypz8eYhfXGrUDyUezm8T7v/UnB5gINzv3YpCdsn+k9cDovu VnerG8sManB9B5tGHTTIzcH7o37C35X0V2ZL56NGRZfTtnl5z1f+kN4IyB/qdGirvRepWqxAM7t 9CBxed+hd7Ckl668umeSPfdlGctXSKbwJnmAtsCNykxRMz9wz18jcI+jvFj1H0XmG4VGOSWyQfP VesowH2unT3NhCFdWdGPK03cmV19VfwmxQtY+WH31Q2Y= X-Google-Smtp-Source: AGHT+IHeguv07zn7PopxqLwKtI4bjCY6HilLCIVsEeepBICMgZEldOzEBMuM0jpND7zvDyOaAtxwEQ== X-Received: by 2002:a05:600d:4270:b0:46f:b42e:e38f with SMTP id 5b1f17b1804b1-46fb42ee4a2mr103687425e9.19.1760436181915; Tue, 14 Oct 2025 03:03:01 -0700 (PDT) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb489197dsm239615305e9.10.2025.10.14.03.02.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 03:03:00 -0700 (PDT) From: Abel Vesa Date: Tue, 14 Oct 2025 13:02:30 +0300 Subject: [PATCH v3 4/4] phy: qcom: edp: Add Glymur platform support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-phy-qcom-edp-add-glymur-support-v3-4-2772837032ef@linaro.org> References: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> In-Reply-To: <20251014-phy-qcom-edp-add-glymur-support-v3-0-2772837032ef@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=12666; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=YCJPvHG7Gmp3ymjunk6DqHGq3+Tdfwwne9NOLTKD9es=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBo7h/JjjIjaHSwGKSgmflocKTmwjb/ohy4+po2G U9kVJUG8l2JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaO4fyQAKCRAbX0TJAJUV Vg2cD/9V/u7etH9Mbh1CPU1z6p+HzaNu2/UDHWCtwEHB7/3FsOYYGmKeUVbi0/ouwPYuKqWs82X smRwLhhox/ppQflraWunMREb4V5XkUe06+9NqLj8maE/C1Tom20iX6rT8Xx9uIpiRSLsXanFgFY h3oc1O9dft1fyKBm9JjyCEU8QoGHW3tSamLVFid7zj/v+W9xl9RGE8MD0KxUCpHHRcW2g4wd/4C zosxKvPfzBMz9nTU1PElxII6dm0kvkJDlKWc0yF+XQC9XDQelYxRpmu1cRpRb1AYTwwuclmACKS xj4f3g8v3XxjhVlgIKSFfPLwhvUC5Aj+2OuO+rHghoT8YO2GOEl+q5JbHGphxmgrWpe3pvdz9To p2a3nOGd7pPLQs0jZPOxb/zMEdLvUrX+VOcU7Zg5gx0e+DrgTLuwR+1q6cRWGRj2HHU2nqwerql s8wtn7heWSR3lUseppxCWhpwJWRh9KpqYAtSv6Cc4DTXhcTPMljAiUh7oFB+sz1zK6DYu0zyIgc ohmNgNOxiD7fpzIsMwWIXu/FGN3KGDMKeK5mryipXEM0KRvCTVl5tnu7MAaa8YzUQEn61ARMSJD b4cLADxiz1o54xqVfp39vMD9X1XvYaJJoUMWaJAswqxsk67dz2wGgsiIE6E0ghcpaP4up/4vA+b 6rSO0zwg353/okA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Qualcomm Glymur platform has the new v8 version of the eDP/DP PHY. So rework the driver to support this new version and add the platform specific configuration data. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 230 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 224 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 7b642742412e63149442e4befeb095307ec38173..53872d1a2965ad014e6eae309cf= 93dde815e394a 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -26,6 +26,8 @@ #include "phy-qcom-qmp-qserdes-com-v4.h" #include "phy-qcom-qmp-qserdes-com-v6.h" =20 +#include "phy-qcom-qmp-dp-qserdes-com-v8.h" + /* EDP_PHY registers */ #define DP_PHY_CFG 0x0010 #define DP_PHY_CFG_1 0x0014 @@ -76,6 +78,7 @@ struct phy_ver_ops { int (*com_power_on)(const struct qcom_edp *edp); int (*com_resetsm_cntrl)(const struct qcom_edp *edp); int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp); + int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); }; @@ -83,6 +86,8 @@ struct phy_ver_ops { struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; + int aux_cfg_size; + const u8 *vco_div_cfg; const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; @@ -185,6 +190,10 @@ static const u8 edp_phy_aux_cfg_v4[10] =3D { 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; =20 +static const u8 edp_phy_vco_div_cfg_v4[4] =3D { + 0x1, 0x1, 0x2, 0x0, +}; + static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { { 0x05, 0x11, 0x17, 0x1d }, { 0x05, 0x11, 0x18, 0xff }, @@ -210,6 +219,14 @@ static const u8 edp_phy_aux_cfg_v5[10] =3D { 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 }; =20 +static const u8 edp_phy_aux_cfg_v8[13] =3D { + 0x00, 0x00, 0xa0, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x4, +}; + +static const u8 edp_phy_vco_div_cfg_v8[4] =3D { + 0x1, 0x1, 0x1, 0x1, +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -224,7 +241,11 @@ static int qcom_edp_phy_init(struct phy *phy) if (ret) goto out_disable_supplies; =20 - memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); + memcpy(aux_cfg, edp->cfg->aux_cfg, edp->cfg->aux_cfg_size); + + ret =3D edp->cfg->ver_ops->com_clk_fwd_cfg(edp); + if (ret) + return ret; =20 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, @@ -252,7 +273,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 writel(0xfc, edp->edp + DP_PHY_MODE); =20 - for (int i =3D 0; i < DP_AUX_CFG_SIZE; i++) + for (int i =3D 0; i < edp->cfg->aux_cfg_size; i++) writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); =20 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | @@ -345,22 +366,22 @@ static int qcom_edp_set_vco_div(const struct qcom_edp= *edp, unsigned long *pixel =20 switch (dp_opts->link_rate) { case 1620: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[0]; *pixel_freq =3D 1620000000UL / 2; break; =20 case 2700: - vco_div =3D 0x1; + vco_div =3D edp->cfg->vco_div_cfg[1]; *pixel_freq =3D 2700000000UL / 2; break; =20 case 5400: - vco_div =3D 0x2; + vco_div =3D edp->cfg->vco_div_cfg[2]; *pixel_freq =3D 5400000000UL / 4; break; =20 case 8100: - vco_div =3D 0x0; + vco_div =3D edp->cfg->vco_div_cfg[3]; *pixel_freq =3D 8100000000UL / 6; break; =20 @@ -398,6 +419,11 @@ static int qcom_edp_phy_com_resetsm_cntrl_v4(const str= uct qcom_edp *edp) val, val & BIT(0), 500, 10000); } =20 +static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp) +{ + return 0; +} + static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) { /* Turn on BIAS current for PHY/PLL */ @@ -530,6 +556,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, }; @@ -537,17 +564,23 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = =3D { static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v5), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -555,6 +588,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cf= g =3D { static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; @@ -734,10 +769,192 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = =3D { =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v4), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 +static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 step1; + u32 step2; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 8100: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + case 5400: + step1 =3D 0x5b; + step2 =3D 0x02; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1); + writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1); + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2); + writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0); + + return 0; +} + +static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 div_frac_start2_mode0; + u32 div_frac_start3_mode0; + u32 dec_start_mode0; + u32 lock_cmp1_mode0; + u32 lock_cmp2_mode0; + u32 code1_mode0; + u32 code2_mode0; + u32 hsclk_sel; + + switch (dp_opts->link_rate) { + case 1620: + hsclk_sel =3D 0x5; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x37; + lock_cmp2_mode0 =3D 0x04; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 2700: + hsclk_sel =3D 0x3; + dec_start_mode0 =3D 0x34; + div_frac_start2_mode0 =3D 0xc0; + div_frac_start3_mode0 =3D 0x0b; + lock_cmp1_mode0 =3D 0x07; + lock_cmp2_mode0 =3D 0x07; + code1_mode0 =3D 0x71; + code2_mode0 =3D 0x0c; + break; + + case 5400: + case 8100: + hsclk_sel =3D 0x2; + dec_start_mode0 =3D 0x4f; + div_frac_start2_mode0 =3D 0xa0; + div_frac_start3_mode0 =3D 0x01; + lock_cmp1_mode0 =3D 0x18; + lock_cmp2_mode0 =3D 0x15; + code1_mode0 =3D 0x14; + code2_mode0 =3D 0x25; + break; + + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL); + writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1); + writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1); + writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0); + writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START= 2_MODE0); + writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START= 3_MODE0); + writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1); + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER); + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL); + writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN); + writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0); + writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0); + + writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MOD= E0); + writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MOD= E0); + + return 0; +} + + +static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL); + + return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); +} + +static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp) +{ + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1); + + return 0; +} + +static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp) +{ + /* Turn on BIAS current for PHY/PLL */ + writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); + + return 0; +} + +static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp) +{ + u32 val; + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + edp->edp + DP_PHY_PD_CTL); + writel(0xfc, edp->edp + DP_PHY_MODE); + + return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v8, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v8, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v8, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, + .com_configure_pll =3D qcom_edp_com_configure_pll_v8, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, +}; + +static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v8, + .aux_cfg_size =3D ARRAY_SIZE(edp_phy_aux_cfg_v8), + .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .ver_ops =3D &qcom_edp_phy_ops_v8, +}; + static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -1133,6 +1350,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { + { .compatible =3D "qcom,glymur-dp-phy", .data =3D &glymur_phy_cfg, }, { .compatible =3D "qcom,sa8775p-edp-phy", .data =3D &sa8775p_dp_phy_cfg, = }, { .compatible =3D "qcom,sc7280-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, --=20 2.48.1