From nobody Sun Dec 14 13:56:08 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C7BD314A80; Tue, 14 Oct 2025 14:07:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760450855; cv=none; b=Ji3Q4BFRdBIbytbL8tamoUIo8PzTGFQ9ohcjR54F3i/A5jxlPHJjVxg0cR2C9EB60ZJkzI36W7Rfu9qcqlP8xTmVwKPLNR/QNl0HNsjMj3M2qnXAKeQEx/5bx6eRWSLfsGiR9uNOujF8OH6Yq8kgoS6t8GfFay+UXH748lBzVhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760450855; c=relaxed/simple; bh=2dJZXPYG1xQ3gbuaV0FdEHXBXGZAABm+2T16rtqoQ/I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qvYalPNfF3yu6wj1pZPB7ADK8EW84Y5RxMzqvDJJdYJQv4xjDfQetfhHh5FdGIDbbFwaWe49UZSiXp548Y7Vw0LZDKDFoXI0aVdqYHMpZqwa2gqAg/VS/eSDbc6rc0WKjAifcaKMpAVLuJ7+Xo9hxZ9gaz2nLnKTOUOotutRa04= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=Wp3gUdDW; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=WTBqbjuP; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="Wp3gUdDW"; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="WTBqbjuP" DKIM-Signature: v=1; a=rsa-sha256; s=202507r; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1760450670; bh=RkTGnMYqBliOzt7ckmePrnL 8uJNbGkOPox9oe6/eVpQ=; b=Wp3gUdDWaw/eyfdeatQhFzVgwrgswL3quckT59KanGF8i1kbTV ztCVzWsBDhK96h3MydF4EcK60RGprYhKpGRcnV5z404OGSph3jfHIP9dJiUEH0ny/DdxsVoAuBM 3RMqnWj+IJBo9rQFiQZCI5zZrPFZ1eAPDPUhp6DuBLqQVcOHm5s2xaeApi85qq2+lU+qN8Xsd2U D5snQMdQXEi4pV7S748ur2kGqu3ofhjgP7sPYt6gGt8MdZS9h9VF3UWfBgath+tPAL3UbNV68/k jbKjzYsdeKfeD98lmc2qIp0E4mZeyryPpWkFJNUeW258eWtE0ZIY0K3gDfMZVFz9HBQ==; DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1760450670; bh=RkTGnMYqBliOzt7ckmePrnL 8uJNbGkOPox9oe6/eVpQ=; b=WTBqbjuPtMhDn8xGemIwQrE1itD82bEgqT27dAj+CNoUPkpoQF nrcsHwjjWEcepvPNLhiv5sPjZzN6IAV8xmCw==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Tue, 14 Oct 2025 16:04:24 +0200 Subject: [PATCH v10 1/3] arm64: dts: qcom: Add initial support for MSM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-msm8937-v10-1-b3e8da82e968@mainlining.org> References: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> In-Reply-To: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Adam Skladowski , Sireesh Kodali , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dang Huynh , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760450666; l=50076; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=1PrLIfsSbqj3r9PkTbu6LwGpcJSEgWw5Ow+QZoiDKa4=; b=2b0exF87BpUFmRhB6DtomuTKTGKYzPPNy+k6Vj9liVKVGRpSf1emPesFGbxLXidT/niDZHxe4 06U6dmCsbd5CKXXy2dCzWk+Njt95uNRX/eQDD5Bc5e6Bk8wATiunW2R X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dang Huynh Add initial support for MSM8937 SoC. Signed-off-by: Dang Huynh Reviewed-by: Dmitry Baryshkov Co-developed-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Konrad Dybcio Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/msm8937.dtsi | 2133 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2133 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qc= om/msm8937.dtsi new file mode 100644 index 000000000000..b93621080989 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -0,0 +1,2133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@100 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@102 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@103 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8937", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", + "bus", + "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + device_type =3D "memory"; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + qseecom_mem: reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + rmtfs@92100000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id =3D <1>; + }; + + adsp_mem: adsp { + size =3D <0x0 0x1100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8937-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs1 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8937", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8937", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs1 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apcs1 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + mboxes =3D <&apcs1 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs1 13>, <0>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8937-qfprom", "qcom,qfprom"; + reg =3D <0x000a4000 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base1: base1@1d8 { + reg =3D <0x1d8 0x1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg =3D <0x1d9 0x1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg =3D <0x1d9 0x2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg =3D <0x1da 0x2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg =3D <0x1db 0x1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg =3D <0x1dc 0x1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg =3D <0x1dc 0x2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg =3D <0x1dd 0x2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg =3D <0x1de 0x1>; + bits =3D <2 6>; + }; + + tsens_base2: base2@1df { + reg =3D <0x1df 0x1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@210 { + reg =3D <0x210 0x1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg =3D <0x210 0x2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg =3D <0x211 0x1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg =3D <0x211 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg =3D <0x212 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg =3D <0x213 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg =3D <0x214 0x1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg =3D <0x214 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg =3D <0x215 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg =3D <0x216 0x2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg =3D <0x217 0x1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@230 { + reg =3D <0x230 0x1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg =3D <0x230 0x2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg =3D <0x231 0x2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg =3D <0x232 0x1>; + bits =3D <2 6>; + }; + + gpu_speed_bin: gpu-speed-bin@201b { + reg =3D <0x201b 0x1>; + bits =3D <7 1>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", + "ahb", + "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", + "por"; + status =3D "disabled"; + }; + + rng@e3000 { + compatible =3D "qcom,prng"; + reg =3D <0x000e3000 0x1000>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts =3D ; + interrupt-names =3D "uplow"; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + cs-pins { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins =3D "gpio79", "gpio80"; + function =3D "wcss_wlan"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins =3D "gpio78"; + function =3D "wcss_wlan0"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins =3D "gpio77"; + function =3D "wcss_wlan1"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins =3D "gpio76"; + function =3D "wcss_wlan2"; + drive-strength =3D <6>; + bias-pull-up; + + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8937"; + reg =3D <0x01800000 0x80000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; + clock-names =3D "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8937", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names =3D "mdss_phys", + "vbif_phys"; + ranges; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + status =3D "disabled"; + + mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8937-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + iommus =3D <&apps_iommu 0x15>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + mdp5_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a94000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi0_opp_table>; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94400 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@1a96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a96000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc MSM8937_BYTE1_CLK_SRC>, + <&gcc MSM8937_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>, + <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>, + <&gcc MSM8937_GCC_MDSS_ESC1_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi1_phy>; + + operating-points-v2 =3D <&mdss_dsi1_opp_table>; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + + mdss_dsi1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-505.0", "qcom,adreno"; + reg =3D <0x01c00000 0x40000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + #cooling-cells =3D <2>; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc MSM8937_GCC_OXILI_TIMER_CLK>, + <&gcc MSM8937_GCC_OXILI_AON_CLK>; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + + iommus =3D <&adreno_smmu 0>; + + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz =3D /bits/ 64 <216000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_nom_plus>; + }; + + opp-450000000 { + opp-hz =3D /bits/ 64 <450000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + }; + }; + + adreno_smmu: iommu@1c40000 { + compatible =3D "qcom,msm8996-smmu-v2", + "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg =3D <0x01c40000 0x10000>; + + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + ; + #iommu-cells =3D <1>; + + clocks =3D <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_OXILI_AHB_CLK>; + clock-names =3D "bus", + "iface"; + + power-domains =3D <&gcc MSM8937_OXILI_CX_GDSC>; + }; + + apps_iommu: iommu@1e20000 { + compatible =3D "qcom,msm8937-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", + "bus"; + + qcom,iommu-secure-id =3D <17>; + + #address-cells =3D <1>; + #iommu-cells =3D <1>; + #size-cells =3D <1>; + + /* VFE */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, + <0x07824000 0x800>; + reg-names =3D "hc", + "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + pinctrl-0 =3D <&sdc1_default>; + pinctrl-1 =3D <&sdc1_sleep>; + pinctrl-names =3D "default", + "sleep"; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x500>, + <0x07864000 0x800>; + reg-names =3D "hc", + "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", + "sleep"; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 2>, + <&blsp1_dma 3>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", + "sleep"; + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, + <&blsp1_dma 7>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c3_default>; + pinctrl-1 =3D <&blsp1_i2c3_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_spi3_default>; + pinctrl-1 =3D <&blsp1_spi3_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 10>, + <&blsp1_dma 11>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c4_default>; + pinctrl-1 =3D <&blsp1_i2c4_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1d000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <10>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp2_dma 4>, + <&blsp2_dma 5>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp2_i2c1_default>; + pinctrl-1 =3D <&blsp2_i2c1_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp2_dma 6>, + <&blsp2_dma 7>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp2_spi2_default>; + pinctrl-1 =3D <&blsp2_spi2_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", + "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + wcnss: remoteproc@a204000 { + compatible =3D "qcom,pronto-v3-pil", "qcom,pronto"; + reg =3D <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names =3D "ccu", + "dxe", + "pmu"; + + memory-region =3D <&wcnss_mem>; + + interrupts-extended =3D <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains =3D <&rpmpd MSM8937_VDDCX>, + <&rpmpd MSM8937_VDDMX>; + power-domain-names =3D "cx", + "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-0 =3D <&wcnss_pin_a>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + wcnss_iris: iris { + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs1 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss_ctrl: wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&wcnss>; + + wcnss_bt: bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", + "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + clocks =3D <&sleep_clk>; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + thermal-sensors =3D <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors =3D <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + q6-thermal { + thermal-sensors =3D <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens 4>; + + cooling-maps { + map0 { + trip =3D <&cpuss1_alert0>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu4_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu5_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu6_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu7_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&cpuss0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss0_crit: cpuss0-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 10>; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; + --=20 2.51.0 From nobody Sun Dec 14 13:56:08 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C81423148B5; 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1760450672; bh=bs3pDuZF7k0IowhT2GCL0eg O4YvxtwPIPG+lhIu5moA=; b=h30FJP+ip4dEkH/Jff3KdHwdN+vJvU6dB+LfknzUOokJe8hZB8 G2URqHWNdt9wBKC5Uz4/84ONbPnjigI9BEAg==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Tue, 14 Oct 2025 16:04:25 +0200 Subject: [PATCH v10 2/3] dt-bindings: arm: qcom: Add Xiaomi Redmi 3S Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-msm8937-v10-2-b3e8da82e968@mainlining.org> References: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> In-Reply-To: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Adam Skladowski , Sireesh Kodali , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760450666; l=1121; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=qXgvWo/arDfz4FQGxhmSd+d+QgpyevLvyROQW/TPwQo=; b=KQDScanAjFKMO8WzDyf//3eLkzU7mYF2IuY0W2qnqGctb6YwYg75o445X1+D+2aljXYfz4S83 uYr3TK7uTgkADB25RqKgSowWJXwMrczqGSJrs7t8TrBEk7+u1YKd9Gn X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document Xiaomi Redmi 3S (land). Add qcom,msm8937 for msm-id, board-id allow-list. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 18b5ed044f9f..639a59d991de 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -191,6 +191,11 @@ properties: - xiaomi,riva - const: qcom,msm8917 =20 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - flipkart,rimob @@ -1167,6 +1172,7 @@ allOf: - qcom,apq8094 - qcom,apq8096 - qcom,msm8917 + - qcom,msm8937 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 --=20 2.51.0 From nobody Sun Dec 14 13:56:08 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DD12FC025; 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1760450674; bh=O4fWC50ZLt5I0sbr+hcbROY yemffhMxyuRKNrY4SvvA=; b=LkLUh0v2adm8vwfQN/WvJxww0GkKlyBaUJFTTtxgfhuvfD9EAI PlIYzRdRCEPk2WTEdDIhdwPYyF1IGSho/xDA==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Tue, 14 Oct 2025 16:04:26 +0200 Subject: [PATCH v10 3/3] arm64: dts: qcom: Add Xiaomi Redmi 3S Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-msm8937-v10-3-b3e8da82e968@mainlining.org> References: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> In-Reply-To: <20251014-msm8937-v10-0-b3e8da82e968@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Adam Skladowski , Sireesh Kodali , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760450666; l=9506; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=y3mg29WwTjjWm6oB1v2X2cXXOgsjXz/Ncrn8XkWXjW0=; b=ZMyevEYpHIjVWjP1//12N3G7qDlUhRMWKxMBE2RQFmldrEFfTOktZcqqhCJSaI7YVSx8nBXfI 9Lf/pSqS9PNCMEaO8gfjUwnn5cgrIig6r7XkC817jqOoNlerTfHVBzh X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add initial support for Xiaomi Redmi 3S (land). Reviewed-by: Konrad Dybcio Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts | 381 +++++++++++++++++++= ++++ 2 files changed, 382 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 296688f7cb26..3d3aef6a5ed7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8929-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8937-xiaomi-land.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-longcheer-l9100.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-samsung-a7.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts b/arch/arm64/= boot/dts/qcom/msm8937-xiaomi-land.dts new file mode 100644 index 000000000000..91837ff940f1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Barnabas Czeman + */ +/dts-v1/; + +#include +#include +#include + +#include "msm8937.dtsi" +#include "pm8937.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model =3D "Xiaomi Redmi 3S (land)"; + compatible =3D "xiaomi,land", "qcom,msm8937"; + chassis-type =3D "handset"; + + qcom,msm-id =3D ; + qcom,board-id =3D <0x1000b 1>, <0x2000b 1>; + + aliases { + mmc0 =3D &sdhc_1; + mmc1 =3D &sdhc_2; + }; + + battery: battery { + compatible =3D "simple-battery"; + + charge-full-design-microamp-hours =3D <4100000>; + constant-charge-current-max-microamp =3D <1000000>; + voltage-min-design-microvolt =3D <3400000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "framebuffer0"; + + framebuffer0: framebuffer@8dd01000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + width =3D <720>; + height =3D <1280>; + stride =3D <(720 * 3)>; + format =3D "r8g8b8"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains =3D <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&gpio_keys_default>; + pinctrl-names =3D "default"; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + irled { + compatible =3D "gpio-ir-tx"; + gpios =3D <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; + + reserved-memory { + reserved@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer: memory@8dd01000 { + reg =3D <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status =3D "okay"; + + led-controller@45 { + compatible =3D "awinic,aw2013"; + reg =3D <0x45>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + vcc-supply =3D <&pm8937_l10>; + vio-supply =3D <&pm8937_l5>; + + led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + }; +}; + +&blsp1_i2c3 { + status =3D "okay"; + + touchscreen@3e { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x3e>; + + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&pm8937_l10>; + iovcc-supply =3D <&pm8937_l5>; + + pinctrl-0 =3D <&tsp_int_rst_default>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <720>; + touchscreen-size-y =3D <1280>; + }; +}; + +&pm8937_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pm8937_spmi_regulators { + /* APC */ + pm8937_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pmi8950_wled { + qcom,num-strings =3D <2>; + qcom,external-pfet; + qcom,current-limit-microamp =3D <20000>; + qcom,ovp-millivolt =3D <29600>; + + status =3D "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible =3D "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + + vdd_l1_l19-supply =3D <&pm8937_s3>; + vdd_l2_l23-supply =3D <&pm8937_s3>; + vdd_l3-supply =3D <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply =3D <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + regulator-allow-set-load; + regulator-system-load =3D <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&sdc2_cmd_default { + drive-strength =3D <12>; +}; + +&sdc2_data_default { + drive-strength =3D <12>; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8937_l8>; + vqmmc-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&pm8937_l11>; + vqmmc-supply =3D <&pm8937_l12>; + pinctrl-0 =3D <&sdc2_default &sdc2_cd_default>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <20 4>; + + gpio_keys_default: gpio-keys-default-state { + pins =3D "gpio91"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins =3D "gpio64", "gpio65"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&wcnss_iris { + compatible =3D "qcom,wcn3620"; + vddxo-supply =3D <&pm8937_l7>; + vddrfa-supply =3D <&pm8937_l19>; + vddpa-supply =3D <&pm8937_l9>; + vdddig-supply =3D <&pm8937_l5>; +}; + +&wcnss_mem { + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.51.0