From nobody Thu Dec 18 12:27:00 2025 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7B0D3009DB for ; Tue, 14 Oct 2025 15:04:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760454291; cv=none; b=Dp4TbzxyV7gUHwH03oFAS/MOpWUn87xyVfSW+xhlUpc21H89PUxX0smedlns6a5s0Yrpj7tui24qRVbH5kXLkdhXRZDQqJH74VNs6ZFGD8gahZEzJdYMIaMOAWB/EQbuJWPdyvTprqfaeVcLQecEwNJM91MNgLTLjmqBGdY9vTs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760454291; c=relaxed/simple; bh=qBtg7GvHWTTjyZPMcecSa1H/np7c9hEJRJGdlfAVn88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QUU7yA/iIvLtipNks9iJKQsQc6n6dmWp9ue701dHUBO9nBCcwH8iztwSjEvdJYnksUGJMDdLwIobcmjGBHCQ9JrQS/5JaohdamOPHThTI1l/vL59jjxNT5VYBRi6iKu9oY3onrt6eVYiiw1KPPSClkCiaD6tU7r1+thDKXH9eKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dx4MzJdl; arc=none smtp.client-ip=209.85.210.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dx4MzJdl" Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-77f1f29a551so6969259b3a.3 for ; Tue, 14 Oct 2025 08:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760454288; x=1761059088; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M7yamUBkHwJEe6SZQP6ugity7ctW5TH+GzI9VTk5Vx4=; b=dx4MzJdlSgzj73VBPoqtGLUDfQUJ/b+GIwt6rQPHqCHoRhogB0w/3t19AUKDxgkBTh L6Kzsew0WwPRYj/mUAWvVil9ZKN2oDSNiKSQQ6V7aql4oCERuClWjMk+NCYYbG4hIJVR i1i9+gQ7uvkYPp0BI5mYGl3vQ2FTIMd2v+HdpdOI1wQF1BFjh80CnNhaKdPaJdqRGKLg fUiyT1xkzNdP5azh8RulU0QD8TKH0rmxlvyaXlZLRKktz0I35SehfRDHV1EUGqSpg6kt +id9rl5Gp0xgI3POm+ES9H+UwV1ttzuIoIfVJvFctJG8HoYFbDct9uwTx2vcaABsJ05T i8Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760454288; x=1761059088; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M7yamUBkHwJEe6SZQP6ugity7ctW5TH+GzI9VTk5Vx4=; b=KVIXm2998ikHP2j7O92V5lUEbs9XaOJIWupWDBTpOs/4PSNJR9LThIbwayRvIrO3Or e26aAtGFOXJE2lJD4d31BlKYHxJmWfzELV/PfJZ21LUGR19VE3ITrKnIkDEaVoHuxSML t+DUy5vVYtEXt0ubkYxdIKoblqzXDZKG4Zrpo0jqm2ZbYVtWZp88n0aGUllvs0OXeMn7 J4tmQKKMlLX3HigTScXfwoqUJIz2YGEGaHAkODyviIT/S6CaFKRppWeqtFMFaqU78PJV FOEGLSNMjsk1+TKA8/8NNV/M2NlsRDQInbQ+d//DLbraOv6nBJBRlrnf57vmTDMDEN4o fNnw== X-Forwarded-Encrypted: i=1; AJvYcCWuxJ6PrJPgSJACwP1Q6V9zUWX7U/VHFDQUxo8kapf5gae1giDDL1pois0mCj/8Gs8NHCQuDnQW/YSPQsk=@vger.kernel.org X-Gm-Message-State: AOJu0Yw7i+MWwu+v3XNBmDlDUvZcRTj2oCvnCqJWe5/zLF4FaYUmUIAV dnPutOO/bILGwwqSgBwuT/euH2kyB8m+8x92sqtrW32TbetG2eEm0V6I X-Gm-Gg: ASbGncsk/vkzzalxja51th3PxXziA7iWeICLx4a+c3EsnAQ27EFsu8Yij5jxJvIJJLP AIJWwicOzUVK59bAkHqH4ZfMfbFf8THyGr798YGhZsc/wQzo+uz5lOh3+gEs5J6BS1CbZv47n6d wbjhlTPiSdbOnYkayqxVAff5FWAPy9SEiUnH0o76DDdDkO2E5rFhz71GYIh1MYDFbcRsO0M3Zf4 N9ILPvWUnqJmgUr9ekNsHegu5ekSLwOR/QUwNzU6zCkbb5h8KEA3BeaFWGh2wli/m6eDwEnWvWg kKVmeAh/GbG3u/Lrl0ck0xn7ywUxprwWn9JAlC4U6eNRgPz+/vh+lqvUq4ZQSEkPpLKGzLmTjXy QdHMkb0YZbRg/aVhSYZ1CgxcvuhIYgc9+m87Kynn81ak= X-Google-Smtp-Source: AGHT+IEww9I99W8/PZygGRJxzMIg2YqHkGHY82OfCvVnBhXsjjq3b+IaBaRZcgRXbdQmeoBXsMnnHA== X-Received: by 2002:a17:902:f60c:b0:25d:1640:1d59 with SMTP id d9443c01a7336-290273564d2mr290664605ad.8.1760454287769; Tue, 14 Oct 2025 08:04:47 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-33b61a1d3cfsm16258161a91.2.2025.10.14.08.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 08:04:47 -0700 (PDT) From: Nick Chan Date: Tue, 14 Oct 2025 23:02:41 +0800 Subject: [PATCH RESEND v8 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-apple-cpmu-v8-8-3f94d4a2a285@gmail.com> References: <20251014-apple-cpmu-v8-0-3f94d4a2a285@gmail.com> In-Reply-To: <20251014-apple-cpmu-v8-0-3f94d4a2a285@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=qBtg7GvHWTTjyZPMcecSa1H/np7c9hEJRJGdlfAVn88=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBo7mZtwuUXxGp+bEBMOFw0fOI5hasyCnTBVZXw6 pDTgJvyopeJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaO5mbQAKCRABygi3psUI JDwjD/0VqIUZw2bmdEwt1IFvW/89NeDCZCFTK94wyJhIDVELyromSUGE4R8oT+VeLtp8AU0qd1h S/rLwN4iLrya/4cMTsD5t28OJw079ZEDtCdTksyIHImDHlQ0cNi/rylo8AL42cEDcimwT4B1C+i IDojSi2Nqd4TK6Ftwu/weJxUCVcu0m/jqOxg8lGw420K3rkPZy3uNJVpH5xwNGXoEeZFkYWd+qs rSPdHLvSQi+tF+XL1HgwB7EE1CJX30tmPVOsIftP0HoPjNHRUH9a0q2J8c9LWToKupquifcxTpZ fRdKBu1JgDcbfxD/tQ17F2/fQ5VfQ8vU9Pboyg8ohNws1uoduWOr6lT1E9bCqaef6j0BGgF65xk 5Ke0Ll4j3TWtRNv/atT/1A+a81c0VCw2lalXMEDXFPFn6/uOl5JrW4f78AlRUFHwcjqfjuNyNjQ juSZeshe0PjEgmAWAvBpbVskVXkyTc9M6ZM3Aq1agZqbUROnNnsUQ3TyME6qpTUtyejQH6vqycU Rn91jiSRyHBbS/Kb/Cmo0MuYND47ojnHFgu0y0HYdaG1H9b8aaq62lDbbE7u7NWzBAtKrofPNHO RMdME2nFxAxfe1xAOoAADNnaRCeDpV+Ss0UW1qphxRflYWBEakuNR+nT/kgX7DK9yXEeQYGIEai GdOWoBwiEeS8M5Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index d0362a1813788776f4210523efe33a3018cfef2a..afcf7c951379698ceff21c1a99c= ca31b3a6177b1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -521,6 +678,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,6 +707,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -578,6 +746,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -623,6 +796,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -673,6 +851,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -722,6 +911,7 @@ static const struct of_device_id m1_pmu_of_device_ids[]= =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); --=20 2.51.0