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Tue, 14 Oct 2025 08:05:01 -0700 (PDT) From: Nick Chan Date: Tue, 14 Oct 2025 23:02:45 +0800 Subject: [PATCH RESEND v8 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-apple-cpmu-v8-12-3f94d4a2a285@gmail.com> References: <20251014-apple-cpmu-v8-0-3f94d4a2a285@gmail.com> In-Reply-To: <20251014-apple-cpmu-v8-0-3f94d4a2a285@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7991; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=eXvZmBK39TeWTus25bvyHnZagmjkYHmZXICDGfTJwOc=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBo7mZuzzbPmgTQISWzTZFHaZ8+HzyI+1/oresCU kEgfpRygsaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaO5mbgAKCRABygi3psUI JNsyD/9dPq6Gga0MhY1GAxBVjmCR0x+5S77Q6OZjp2t53U/WNUAerTGP2FRE2s2sf8/igr1VuTP p1KHVV2qW1EHUjdinEQcUVl4HBWo/BbZ7VYzpzuRDEAg75pW+NUMlFZYFz6KoQaR65iMBqNcg51 zhiFuccPlfJ9Q7L8Qe7kYRksVhSP3TSKF5xoJzIJZrN8qcySHYtpPZ+uVDCEgG/nfygrbMcSizb cBazO8x51IR/cCCWH8mL7jRjpdlHBVzl0tKMR1pWfag6fBeRbtRDj+a7qWQotRSOb0do66ZWWZa jm4IfrW88LA8n8xvV41Xoi17euLqrUerlmRth1LjV0VkcTGat1jsoFYf/GCoPBzbfqNs01QYZNO EXMQ2EDKctHiCxNjKNJkkoGClg4pAcRsdJNmEYkNFPySpJY7DdIsm8sDD4emtmovHpWHIjZtZgu VNPrzxUNwBIzPCiuHW9xIu8eICSCIYx71nmdT72LUvyDo3MifjNw/qT9oghLaRGCuQDD9ZwjhHd AdC8lZkLjomNFilb8PI1W8HYS1APFTfqKoQycY0/iYC2Q4UWFiPWSRrr+7choM0hqvVNPKnRvgv BowxRznKIbSC8cwFMN2P/OFJv0jpViWu/KfgK3Gcw3SQEyo7DFwEFp7qseCUqA3Q+ZK4fJlc0sg ELaC8ubGKnTsNZA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 37ca7e99aaad97526c468d3c98ec7ce4fe115763..31fe89c928364719ee0d7101128= 6a91adaf6b99f 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_A32 =3D 0x8a, + A11_PMU_PERFCTR_INST_T32 =3D 0x8b, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1020,6 +1127,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1231,6 +1344,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1280,6 +1415,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.51.0