From nobody Fri Dec 19 19:01:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F98F30F932; Tue, 14 Oct 2025 11:55:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760442912; cv=none; b=BMON3Jbu9fkZrNzJKjk04rGi0MJ+SM9k3qhgZgHwewStk1zi8WGEgoz9i80sQMkI1bnVSFB/TloIUFhjWwiFnfb6cOgfYSwFahAKYbI2H6l3WyR5a+Q0YsfHlut3faR1lYpokB94mssg5RPHRm66WV6YZ90B98la1SOltMi2adg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760442912; c=relaxed/simple; bh=3vsViLjDOPyapy+WokuHpqSNPBuplnGz6KFteCnagIY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HPzbiRF7TnOU9Xa2Sb6ULSB6kDTWI7VUb85ZVuIhv+I/9g7H2gFvjuGqIqpUTqQ0pTe9gP56/3Ud2hi3bf9OVOYNRUUoh5hH2agzJNB9jem+zNuWb+et2cRUa8nMcuoF2u+bPWfuQBSwWUo4I9UqyKVrZQNei29Rp4yOtsgy704= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tMBSgPXz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tMBSgPXz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 170A6C113D0; Tue, 14 Oct 2025 11:55:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760442912; bh=3vsViLjDOPyapy+WokuHpqSNPBuplnGz6KFteCnagIY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tMBSgPXzqEbVeWkphNMjC3Io9D3XdjFLuM9zUzX0s0NF5xUZfqzJzBKFQRlYQODir 3Vri1j4D0c8v3Ecgrl8iiJO7OuLfQmO5AEkutcoj1ZbTPexC426zq++HAJwJin9zvO SkZhmnE5oenkun/tSD9eDlidOtLoIcx/UGJu9fzv5uyKAVeRio8xzhFYZz4YZrmzWA UtgCizzmMOznL0p+C7EiMNIoyjqIVofgcGL/SjwgdzxCa0eko6vR0gYAFUEQHV9fa7 zg1z+YoQRuVTgHiGM6EZ3tzguB8nM0cLygIkj/2UC0PphYYu54mI2DCM/eP/GbD3iY +vfLpnwB6I25A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04263CCD184; Tue, 14 Oct 2025 11:55:12 +0000 (UTC) From: Xiangxu Yin via B4 Relay Date: Tue, 14 Oct 2025 19:54:54 +0800 Subject: [PATCH v3 1/3] dt-bindings: display/msm: Add SM6150 DisplayPort controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-add-displayport-support-to-qcs615-devicetree-v3-1-74ec96ba8144@oss.qualcomm.com> References: <20251014-add-displayport-support-to-qcs615-devicetree-v3-0-74ec96ba8144@oss.qualcomm.com> In-Reply-To: <20251014-add-displayport-support-to-qcs615-devicetree-v3-0-74ec96ba8144@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760442910; l=1330; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=pd0jI9Dkdm+Hpa42+VfaO85gcD6oUV4iAuhBm2NnzVg=; b=T9Ay2vQJQys+PiS/auEth/rqCvivTMPMBuFJy8LLDfdNfmbktbb4a2xxerw+ePdCmFqM7dfI2 9rsJBoOEjhoDFx91FJtM7fuVFMfLuSyJZk1nx/goZ+Olhec9YusWUSM X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Endpoint-Received: by B4 Relay for xiangxu.yin@oss.qualcomm.com/20241125 with auth_id=542 X-Original-From: Xiangxu Yin Reply-To: xiangxu.yin@oss.qualcomm.com From: Xiangxu Yin Describe the DisplayPort controller for Qualcomm SM6150 SoC. Signed-off-by: Xiangxu Yin --- .../devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml | 11 +++++++= ++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml index 9ac24f99d3ada1c197c9654dc9babebccae972ed..935eca23ce6b30b81b3ad778e5f= cacc817a230c3 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml @@ -51,6 +51,16 @@ patternProperties: compatible: const: qcom,sm6150-dpu =20 + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + items: + - const: qcom,sm6150-dp + - const: qcom,sm8150-dp + - const: qcom,sm8350-dp + "^dsi@[0-9a-f]+$": type: object additionalProperties: true @@ -132,6 +142,7 @@ examples: port@0 { reg =3D <0>; dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; }; }; =20 --=20 2.34.1 From nobody Fri Dec 19 19:01:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0C933101C1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251014-add-displayport-support-to-qcs615-devicetree-v3-2-74ec96ba8144@oss.qualcomm.com> References: <20251014-add-displayport-support-to-qcs615-devicetree-v3-0-74ec96ba8144@oss.qualcomm.com> In-Reply-To: <20251014-add-displayport-support-to-qcs615-devicetree-v3-0-74ec96ba8144@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760442910; l=4639; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=OcHxsH0aC7yslXyGK1d8KKcAIWgItEqNh/1KvpqOsJQ=; b=75BrCV+YxlujQdBvrjo/q8LLuulOmbEQIZd1+TBRODvMRcjE/bYAg0UbpgSEeU36Y/1NvetCS sZcnuatSB+vDoGS6vavQPhtXhjRDdFn4dD1fd44qOvGhpPV82EeTklF X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Endpoint-Received: by B4 Relay for xiangxu.yin@oss.qualcomm.com/20241125 with auth_id=542 X-Original-From: Xiangxu Yin Reply-To: xiangxu.yin@oss.qualcomm.com From: Xiangxu Yin Introduce DisplayPort controller node and associated QMP USB3-DP PHY for SM6150 SoC. Update clock and endpoint connections to enable DP integration. Signed-off-by: Xiangxu Yin --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 113 +++++++++++++++++++++++++++++++= +++- 1 file changed, 111 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..36a536cef99a095938f3e18a9b5= e7825308ca426 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -3717,6 +3718,7 @@ port@0 { reg =3D <0>; =20 dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; }; }; =20 @@ -3749,6 +3751,87 @@ opp-307200000 { }; }; =20 + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; + + reg =3D <0x0 0x0ae90000 0x0 0x200>, + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys =3D <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dp0_out: endpoint { + data-lanes =3D <3 2 0 1>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg =3D <0x0 0x0ae94000 0x0 0x400>; @@ -3844,8 +3927,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, - <0>, - <0>; + <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; =20 #clock-cells =3D <1>; #reset-cells =3D <1>; @@ -4214,6 +4297,32 @@ usb_qmpphy: phy@88e6000 { status =3D "disabled"; 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s=20241125; h=from:subject:message-id; bh=/51//v+svjuZY3Iiy6UrPCdt/x4774tlFAIE0Mple+c=; b=7ZeEYtFTY/JFvZVoNFZpXRlV+3nVG0clQ4G2JxYgyOnwoqDD1DhKNyJ6xhgwkBNH/oHfH5zcn /xW0jtlXtAqAnIgbNVJAhCs8PT2QE1/ALr8KqLId0hDUod0WVSSkpCS X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Endpoint-Received: by B4 Relay for xiangxu.yin@oss.qualcomm.com/20241125 with auth_id=542 X-Original-From: Xiangxu Yin Reply-To: xiangxu.yin@oss.qualcomm.com From: Xiangxu Yin Add DP connector node and configure MDSS DisplayPort controller for QCS615 Ride platform. Include lane mapping and PHY supply settings to support DP output. Signed-off-by: Xiangxu Yin --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 30 ++++++++++++++++++++++++++++= ++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 9ac1dd3483b56f9d1652f8a38f62d759efa92b6a..bb0f4b8265e4807e50d067aed8b= 21557d97b20dd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,20 @@ xo_board_clk: xo-board-clk { }; }; =20 + dp0-connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "mini"; + + hpd-gpios =3D <&io_expander 8 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + dp-dsi0-connector { compatible =3D "dp-connector"; label =3D "DSI0"; @@ -423,6 +437,15 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint =3D <&dp0_connector_in>; +}; + &mdss_dsi0 { vdda-supply =3D <&vreg_l11a>; status =3D "okay"; @@ -623,6 +646,13 @@ &usb_qmpphy { status =3D "okay"; }; =20 +&usb_qmpphy_2 { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + &usb_1 { status =3D "okay"; }; --=20 2.34.1