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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF00000140.mail.protection.outlook.com (10.167.244.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9228.7 via Frontend Transport; Mon, 13 Oct 2025 17:37:12 +0000 Received: from titanite-d354host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 13 Oct 2025 10:37:10 -0700 From: Avadhut Naik To: CC: , , , Subject: [PATCH 2/4] EDAC/amd64: Remove NUM_CONTROLLERS macro Date: Mon, 13 Oct 2025 17:30:41 +0000 Message-ID: <20251013173632.1449366-3-avadhut.naik@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251013173632.1449366-1-avadhut.naik@amd.com> References: <20251013173632.1449366-1-avadhut.naik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000140:EE_|LV3PR12MB9330:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ff1b6d7-ee94-460c-a0ac-08de0a7f24c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 17:37:12.6488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ff1b6d7-ee94-460c-a0ac-08de0a7f24c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000140.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9330 Content-Type: text/plain; charset="utf-8" Currently, the NUM_CONTROLLERS macro is only used to statically allocate the csels array of struct chip_select in struct amd64_pvt. The size of this array, however, will never exceed the number of UMCs on the SOC. Since, max_mcs variable in struct amd64_pvt already stores the number of UMCs on the SOC, the macro can be removed and the static array can be dynamically allocated instead. The max_mcs variable and the csels array are used for legacy systems too. These systems have a max of 2 controllers (DCTs). Since the default value of max_mcs, set in per_family_init(), is 2, these legacy system are also covered by this change. Signed-off-by: Avadhut Naik --- drivers/edac/amd64_edac.c | 5 +++++ drivers/edac/amd64_edac.h | 5 ++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 886ad075d222..2391f3469961 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3732,6 +3732,7 @@ static void hw_info_put(struct amd64_pvt *pvt) pci_dev_put(pvt->F1); pci_dev_put(pvt->F2); kfree(pvt->umc); + kfree(pvt->csels); } =20 static struct low_ops umc_ops =3D { @@ -3915,6 +3916,10 @@ static int per_family_init(struct amd64_pvt *pvt) scnprintf(pvt->ctl_name, sizeof(pvt->ctl_name), "F%02Xh_M%02Xh", pvt->fam, pvt->model); =20 + pvt->csels =3D kcalloc(pvt->max_mcs, sizeof(*pvt->csels), GFP_KERNEL); + if (!pvt->csels) + return -ENOMEM; + return 0; } =20 diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index bb6cf4b1ab77..5f61631c8a7d 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -96,7 +96,6 @@ /* Hardware limit on ChipSelect rows per MC and processors per system */ #define NUM_CHIPSELECTS 8 #define DRAM_RANGES 8 -#define NUM_CONTROLLERS 16 =20 #define ON true #define OFF false @@ -347,8 +346,8 @@ struct amd64_pvt { u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ =20 - /* one for each DCT/UMC */ - struct chip_select csels[NUM_CONTROLLERS]; + /* Allocate one for each DCT/UMC */ + struct chip_select *csels; =20 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ struct dram_range ranges[DRAM_RANGES]; --=20 2.43.0