From nobody Fri Dec 19 17:18:43 2025 Received: from mail-il1-f181.google.com (mail-il1-f181.google.com [209.85.166.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AD77313548 for ; Mon, 13 Oct 2025 15:35:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369748; cv=none; b=P5gETOP5p8Qt+SV+NR2dD6RwTVCSWNALoUr4tN/9QMWkWKbZq4T3jagrMejOCjwmmFB+pqwvjNA25/T1uSbenPt9vUH6SMNKuxX2XsvARsHw/emT5BJc5x12aazFyi/XyIXyMH7y4IJQ+0pSlu7wp61ikhII6hwPwTRkenroer0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369748; c=relaxed/simple; bh=4aZka/RAU4QYbrbCdQ/ULFAxcWVzlo5Q0/JoKZooWf0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dTHFqP+VkOArmzWmH0sbWZPIKID07AUuYembJvnzVs+6qCs2UcpMbCQfEh8mj4JEKrY5Tg8a4CehepnLQYw8F/67jSbGp1O6G6HHd/y8jxN9JCDmGjUqpAUsmegHb6rg/BsSG3gxQUw3Oz0zaox5Z6EnVCYXyGY0WbTjhsSrKws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=XB1W3/4Y; arc=none smtp.client-ip=209.85.166.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="XB1W3/4Y" Received: by mail-il1-f181.google.com with SMTP id e9e14a558f8ab-42f91d225c9so17699855ab.0 for ; Mon, 13 Oct 2025 08:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1760369745; x=1760974545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IC7TMG3lk59s+A7a4ImbP9PPZe+ugMZHmrnVEzsSLBc=; b=XB1W3/4YXfKWBN7N8PXR5JDV8WMyWgKcUjwcsdPrgY3tRzgQHMu/rJwOs1ltkB6F6N N5tLw1oQY6kfu7NZlggWYegFYU79szF1kEjW1pBwJ3UoJL9zCywV3YITk9VQlXasp/Nl JhM13S33p6Lj/MudxFuZYEuSYvHdqx6lQAatnIKdKIDpezy1eckO8q/rvEv4ehxXGDOy +kbXv/Wmq43FjKU6rXe6mtEaKBzXpw2yBVJE0CHsX7FPD+uxy4AF6MFBBm6DQU8ZHrww JeKcse3k1zLEbanEEv8upLaRzAh6gla2rYRznl25m6yg0Eo5A6JwftjS59oRUhEbdO7H pitg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760369745; x=1760974545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IC7TMG3lk59s+A7a4ImbP9PPZe+ugMZHmrnVEzsSLBc=; b=JzP02xbevLm+MuJ1VflyrNqF7qihpCr+kRrHu8JIdeyUbb+/N6UTUU4zFr9rPH3xZU VEnwE0N+szlpDtEcFP89dPqFNSQAMQo0BIEQPfhPjmn3wTv7OVvNdJ/w2yz0rsM/otnx eVV5eg6cnNppIbb4lH0M3TGSO7Ub0g+YIHA9R1uvqjVaVPeemxwt4DKhOOLpFYmj1EUT l4/1bJXQJ/38CLh3xaOMwGCBqDZFV4VeCENgTqYRJza/m3HktEVigC3+CHSMGuuri+Ca TdWdG1nYphTZ59vOf2eK1gnMe16wrn2vLihpqb2GJ5xVQrVcAPXfVyEVOLa08ISjE1aR 6C9Q== X-Forwarded-Encrypted: i=1; AJvYcCWVUKuFhTWKlo4ie/MSI2binBXApB39ecLVjbs1eSa+HEG0KjwORTssmJIyc7sEGqQo1IPcv06Oc7Og0rU=@vger.kernel.org X-Gm-Message-State: AOJu0YwelUNaE6HuurADABPKIi+t3x99fPFDXfznaoXKsqAD5Cz4hYGy dOKMXshLq6pQj1/QEI43MOvfFBj36W2wHOdnCS6BjWYpub4cYUjSZlskbwSNmghakhY= X-Gm-Gg: ASbGncsytnT0SQBs8ErOmcqBkz2Q+LRsa532au0oVKIyER+Du2X1EZRs+Yb82dT3f6O ASXgJVJHPP7VT+t+at6Bv3BASbHcXy3b8ZvzE/sIyK+SsP9r1BsAx41+potJu89ZiL9wE0Zj7Ui q7kP3x3hOW1+INFmdmTmdhDLWXfJAe4x24hL9QExBejTXoSzoFwk906o8nzaoAF0N5hPePf2uls 8F3L1w+6bRQs4xy0bN+bDGlZwVkOL+3Jl5EeWnBY9B86LAAAQXKUy8ahNI1oQM0Q8Iyn005gXTw eIWv0EYArITBBlGfgPQ1GuMnCQzlhhGzpBS4EcsL3TPDwD6QM/n5pzj473cNwEaIjvPXJSS/Pyy ILP5y5uJBAQB2OkNjppldewaTaLfELVnxsQxoVtFs4PNutgVV0qvh69WWKgvO5cLvJLDjCdZ+K4 ftenTLtr0RKrKOmWlSfmI= X-Google-Smtp-Source: AGHT+IHjDpApPK7L1lugdyMLdu/ALrQ3dDMp82iS7o9Xm0eHdrN9XhJaFVaUZhe9AQe+NVGfsh4gKw== X-Received: by 2002:a05:6e02:1545:b0:42f:8d6c:f502 with SMTP id e9e14a558f8ab-42f8d6cf905mr216933655ab.0.1760369745223; Mon, 13 Oct 2025 08:35:45 -0700 (PDT) Received: from zippy.localdomain (c-75-72-117-212.hsd1.mn.comcast.net. [75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-58f6c49b522sm3910266173.1.2025.10.13.08.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 08:35:44 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vkoul@kernel.org, kishon@kernel.org Cc: dlan@gentoo.org, guodong@riscstar.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, christian.bruel@foss.st.com, shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, namcao@linutronix.de, thippeswamy.havalige@amd.com, inochiama@gmail.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] riscv: dts: spacemit: PCIe and PHY-related updates Date: Mon, 13 Oct 2025 10:35:24 -0500 Message-ID: <20251013153526.2276556-8-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251013153526.2276556-1-elder@riscstar.com> References: <20251013153526.2276556-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder --- v2: - Added vpcie3v3-supply nodes to PCIe ports - Combo PHY node is now defined earlier in the file (alphabetized) .../boot/dts/spacemit/k1-bananapi-f3.dts | 30 ++++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 151 ++++++++++++++++++ 3 files changed, 214 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 046ad441b7b4e..6d566780aed9d 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -40,6 +40,12 @@ pcie_vcc_3v3: pcie-vcc3v3 { }; }; =20 +&combo_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_3_cfg>; + status =3D "okay"; +}; + &emmc { bus-width =3D <8>; mmc-hs400-1_8v; @@ -100,6 +106,30 @@ &pdma { status =3D "okay"; }; =20 +&pcie1_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + status =3D "okay"; +}; + +&pcie2_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_4_cfg>; + status =3D "okay"; +}; + +&pcie1 { + phys =3D <&pcie1_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + +&pcie2 { + phys =3D <&pcie2_phy>; + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index aff19c86d5ff3..5bacb6aff23f8 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -69,6 +69,39 @@ uart0-2-pins { }; }; =20 + pcie0_3_cfg: pcie0-3-cfg { + pcie0-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie1_3_cfg: pcie1-3-cfg { + pcie1-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie2_4_cfg: pcie2-4-cfg { + pcie2-4-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + pwm14_1_cfg: pwm14-1-cfg { pwm14-1-pins { pinmux =3D ; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 6cdcd80a7c83b..a38c578f24004 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include =20 /dts-v1/; / { @@ -358,6 +359,48 @@ syscon_rcpu2: system-controller@c0888000 { #reset-cells =3D <1>; }; =20 + combo_phy: phy@c0b10000 { + compatible =3D "spacemit,k1-combo-phy"; + reg =3D <0x0 0xc0b10000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "refclk", + "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>, + <&syscon_apmu RESET_PCIE0_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "phy"; + #phy-cells =3D <1>; + spacemit,apmu =3D <&syscon_apmu>; + status =3D "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible =3D "spacemit,k1-pcie-phy"; + reg =3D <0x0 0xc0c10000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>; + clock-names =3D "refclk"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible =3D "spacemit,k1-pcie-phy"; + clocks =3D <&vctcxo_24m>; + clock-names =3D "refclk"; + reg =3D <0x0 0xc0d10000 0x0 0x1000>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible =3D "spacemit,k1-syscon-apbc"; reg =3D <0x0 0xd4015000 0x0 0x1000>; @@ -847,6 +890,114 @@ pcie-bus { #size-cells =3D <2>; dma-ranges =3D <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts =3D <141>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>, + <&syscon_apmu RESET_PCIE0_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "phy"; + device_type =3D "pci"; + num-viewport =3D <8>; + spacemit,apmu =3D <&syscon_apmu 0x03cc>; + status =3D "disabled"; + }; + + pcie1: pcie@ca400000 { + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts =3D <142>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>, + <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "phy"; + device_type =3D "pci"; + num-viewport =3D <8>; + spacemit,apmu =3D <&syscon_apmu 0x3d4>; + status =3D "disabled"; + }; + + pcie2: pcie@ca800000 { + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, + <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; + interrupts =3D <143>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>, + <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names =3D "dbi", + "mstr", + "slv", + "phy"; + device_type =3D "pci"; + num-viewport =3D <8>; + spacemit,apmu =3D <&syscon_apmu 0x3dc>; + status =3D "disabled"; + }; }; =20 storage-bus { --=20 2.48.1