From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 661AE314D3C; Mon, 13 Oct 2025 15:27:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369251; cv=none; b=mx0XuAz2kXdlKVSlrLrTXUAzlAeaJv2sBGRDAs22RJizTBdmieyP9BitC85E6m581YfbmSWufwxcwmxvR5hprGWdUFM83wQqAPcUY1aBU11/pZAwjLC9V6im0rdH1qstORlQslyCuz+8Jr1wniqk/h/SMNuVjk15BGXtuVRqk74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369251; c=relaxed/simple; bh=uV3J+ukDhk15H89nr/D2cVuC6yRnOiEZ9jjzajCXzKA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TiqbhKGbrtCQXfd7Ft6WslQozWUjw+HTD/RvUrXepaG9iRxDFnhQcJNGw2scmrxXMyu6SR5+uBexIL8fLtqxVgkUPThcb2JFib9gN12JHiUy/4WCW/7RJv0fyVv87aNNjSGUUTbhwq9a94tm4dP5iUJhpj9npgmS055IsmZLZX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=nmtuxVis; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="nmtuxVis" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B41404E4106B; Mon, 13 Oct 2025 15:27:27 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 87E226067B; Mon, 13 Oct 2025 15:27:27 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1A6DF102F1D5C; Mon, 13 Oct 2025 17:27:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760369245; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=j9UGTJcWYSBAqp5JJLufyhsbLELsj0ohBAucYdJtZ1o=; b=nmtuxVisKyZjIHulDLUKYBbUvhnneHIQkbm/QxsomgvOTckqW21U/qV47R+cuxQz+aGelx wnXpsK8PmsjCiGxQZzHZlxTC0MVqceM1MQnWiir1XzM2mW5Zqg2+wHIWbcyTk6+a9Sw0tQ cebrpI507mFLHBxz42FMW62LzC0F5snBRpSo+iK4cSNtTXSmoAh3SAOvuqSoQ7VbVP3RmR w8yPk4FfxITQkCtHpiNhdM3BhQOxZkuX2qhLdcAFcOwETotp+WsO7nWo6efRu1lZKfgaAG QOpl+q/f67D2SkrFbst4lxKntnPYWb3jhpsVcr1XYbTf1S+ePVRE3xmErxahCg== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 01/15] mtd: rawnand: sunxi: Remove superfluous register readings Date: Mon, 13 Oct 2025 17:26:31 +0200 Message-ID: <20251013152645.1119308-2-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The register NFC_REG_ECC_CTL was read twice and the result was not used, then a third time with a mask applied. Removing those calls didn't change the behavior. Tested on H616 SoC, scrambling enabled. Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index f6a8e8ae819d..cb12179b63a5 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -623,13 +623,12 @@ static void sunxi_nfc_randomizer_config(struct nand_c= hip *nand, int page, bool ecc) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); - u32 ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL); + u32 ecc_ctl; u16 state; =20 if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL); state =3D sunxi_nfc_randomizer_state(nand, page, ecc); ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK; writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL); From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B023315764; Mon, 13 Oct 2025 15:27:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369253; cv=none; b=iCW/ShdaoDI/WtnA/Y2OVSnHWNmo24wBlm/eQ0Pwij1mle2PFBg8UkaZ+ewKjPzdyt5suSEPw6YiEcAl0BAEJYLctuDI1d7QVe3gHGOFxQDVBETeNHjbJtqrJM2MOGQB7wJslSiCwl9DJce/MNOfhMlP5AMnfCgra4TXrqBXCNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369253; c=relaxed/simple; bh=JaFKXfK/hO/Ws63JMPRrcOyhQl+FFrqJeViUxcZD9Ok=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D3z+rrd/0PWow3qznhu1ZXhTrUGcJRIxns0tn2G7GumAeGsiDBwedT37z6NcKWJ/E+ODvOiF2Wl3fBwC8WYde5cXZprL4sKRM40kPGfWlwYxn8I6tfv1m56ieZQW9XaMvTgLvZWEQlV42Xn1DEX4EFEYST/WedRnVu2Y+Vt4L8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sgJ/Tioz; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sgJ/Tioz" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A036D4E4106C; Mon, 13 Oct 2025 15:27:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 748DE6067B; Mon, 13 Oct 2025 15:27:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A4520102F2273; Mon, 13 Oct 2025 17:27:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760369248; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lhRMyekh2DJFlkcL8J9FV4FVNdXWyGLyYiNOJzk4uhs=; b=sgJ/TiozkUWHDoej/hZQnvGnCB27q+BYY1/WsF9UYQxf8g7N9xHrQQPaPGe0P+KGCWxLqg Du5457Slaqg4ADMLJpgKYMs6lCntdMLUutq2GCltQAO6yWNbVXW6OYNCN/OKBbpEpCm+PI 9qSkubkmPtAyYw8T5fKFBfDBlFWm19kNkJnzEw2HgbnWmSzCNlPLxGiO/4IWAVsLdYm9tx sagdw+MYsGzZbwy8gMeXYQ0kUlueobu2+Z+/+ZgxJN/N7JnmzeArkNUiR0WnpCFOJeX6Q0 5SSG+dyjOP80cBzY4YYC9IkUC9uwPGUchF2tfe/pkrDbNr4MpI7qo2SA9Gs6gQ== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 02/15] mtd: rawnand: sunxi: move ECC strenghts in sunxi_nfc_caps Date: Mon, 13 Oct 2025 17:26:32 +0200 Message-ID: <20251013152645.1119308-3-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" H6/H616 has more ECC strenghts than A10/A23. Move the ECC strenghts array to sunxi_nfc_caps to make it ready for H6/H616 support. No functional change. Signed-off-by: Richard Genoud Reviewed-by: Chen-Yu Tsai --- drivers/mtd/nand/raw/sunxi_nand.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index cb12179b63a5..d3b17d54f04c 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -213,11 +213,15 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(s= truct nand_chip *nand) * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register * @dma_maxburst: DMA maxburst + * @ecc_strengths: Available ECC strengths array + * @nstrengths: Size of @ecc_strengths */ struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; unsigned int dma_maxburst; + const u8 *ecc_strengths; + unsigned int nstrengths; }; =20 /** @@ -1619,9 +1623,9 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, struct nand_ecc_ctrl *ecc, struct device_node *np) { - static const u8 strengths[] =3D { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; struct sunxi_nand_chip *sunxi_nand =3D to_sunxi_nand(nand); struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + const u8 *strengths =3D nfc->caps->ecc_strengths; struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_device *nanddev =3D mtd_to_nanddev(mtd); int nsectors; @@ -1645,7 +1649,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, =20 ecc->strength =3D bytes * 8 / fls(8 * ecc->size); =20 - for (i =3D 0; i < ARRAY_SIZE(strengths); i++) { + for (i =3D 0; i < nfc->caps->nstrengths; i++) { if (strengths[i] > ecc->strength) break; } @@ -1666,7 +1670,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, } =20 /* Add ECC info retrieval from DT */ - for (i =3D 0; i < ARRAY_SIZE(strengths); i++) { + for (i =3D 0; i < nfc->caps->nstrengths; i++) { if (ecc->strength <=3D strengths[i]) { /* * Update ecc->strength value with the actual strength @@ -1677,7 +1681,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, } } =20 - if (i >=3D ARRAY_SIZE(strengths)) { + if (i >=3D nfc->caps->nstrengths) { dev_err(nfc->dev, "unsupported strength\n"); return -ENOTSUPP; } @@ -2167,15 +2171,23 @@ static void sunxi_nfc_remove(struct platform_device= *pdev) dma_release_channel(nfc->dmac); } =20 +static const u8 sunxi_ecc_strengths_a10[] =3D { + 16, 24, 28, 32, 40, 48, 56, 60, 64 +}; + static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .dma_maxburst =3D 4, + .ecc_strengths =3D sunxi_ecc_strengths_a10, + .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .dma_maxburst =3D 8, + .ecc_strengths =3D sunxi_ecc_strengths_a10, + .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8493315D35 for ; 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charset="utf-8" The H6/H616 ECC_ERR_CNT register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index d3b17d54f04c..0285e4d0ca7f 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -46,7 +46,8 @@ #define NFC_REG_ECC_CTL 0x0034 #define NFC_REG_ECC_ST 0x0038 #define NFC_REG_DEBUG 0x003C -#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3) +#define NFC_REG_A10_ECC_ERR_CNT 0x0040 +#define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID 0x00A4 @@ -212,6 +213,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register + * @reg_ecc_err_cnt: ECC error counter register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -219,6 +221,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; + unsigned int reg_ecc_err_cnt; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -790,7 +793,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, return 0; } =20 - tmp =3D readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step)); + tmp =3D readl(nfc->regs + NFC_REG_ECC_ERR_CNT(nfc, step)); =20 return NFC_ECC_ERR_CNT(step, tmp); } @@ -2177,6 +2180,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { =20 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2185,6 +2189,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81CCA315D45 for ; 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charset="utf-8" The H6/H616 USER_DATA register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 0285e4d0ca7f..8f5d8df19e33 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -48,7 +48,8 @@ #define NFC_REG_DEBUG 0x003C #define NFC_REG_A10_ECC_ERR_CNT 0x0040 #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) -#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) +#define NFC_REG_A10_USER_DATA 0x0050 +#define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 @@ -214,6 +215,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register + * @reg_user_data: User data register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -222,6 +224,7 @@ struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; + unsigned int reg_user_data; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -723,8 +726,8 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct = nand_chip *nand, u8 *oob, { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); =20 - sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)), - oob); + sunxi_nfc_user_data_to_buf(readl(nfc->regs + + NFC_REG_USER_DATA(nfc, step)), oob); =20 /* De-randomize the Bad Block Marker. */ if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) @@ -746,7 +749,7 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct = nand_chip *nand, } =20 writel(sunxi_nfc_buf_to_user_data(oob), - nfc->regs + NFC_REG_USER_DATA(step)); + nfc->regs + NFC_REG_USER_DATA(nfc, step)); } =20 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand, @@ -2181,6 +2184,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_A10_USER_DATA, .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2190,6 +2194,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .has_mdma =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_A10_USER_DATA, .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 221A9316195 for ; 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bh=tFIp35uHTqcsmvS0r9Kp5zCwmOEmNlNll/p8ijKVjUE=; b=UwRrx0fZDu564tcgIAHIPHDkw8cVWaoQByE87eSGNddA6EtD1UELRUXpwrjTraQgqR1Huw 6WJ+nDY7aSFQ3bbZWpWDgw7A+gPEqI4Qa+AWFdVQlhVLkHVS4YI2UNNLI+xOdTTpyko1jj /6T2immgCmavYAkOQvRVBlM8sDEOZAUXUroFUWxh/E7K0uDHhVh53IRLDgTZXMRqXgmjxM P8ZqLVJNjTGsJZb0FEh+pc2fcE8oB1KFTX9Tbfp37IwQegD3lZOpTPEiF9ITx6C9eOVnj8 Bj96/pUzQSd+0g2mHInpdamU7Li5C4DU+qR303+op+AwKxz5aEDoUaNJLhr9sQ== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 05/15] mtd: rawnand: sunxi: rework pattern found registers Date: Mon, 13 Oct 2025 17:26:35 +0200 Message-ID: <20251013152645.1119308-6-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" On H6/H616, the register ECC_PAT_FOUND is at its own address, and not part of ECC status register. So, introduce the pattern found register offset in sunxi_nfc_caps, along with its mask. Also, introduce a non compile-time field_get() because FIELD_GET() and u32_get_bits() don't work with non compile-time constant. https://lore.kernel.org/lkml/cover.1739540679.git.geert+renesas@glider.be/ No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 36 ++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 8f5d8df19e33..4cfb5d3e9c06 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -29,6 +29,9 @@ #include #include =20 +/* non compile-time field get */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + #define NFC_REG_CTL 0x0000 #define NFC_REG_ST 0x0004 #define NFC_REG_INT 0x0008 @@ -150,7 +153,13 @@ /* define bit use in NFC_ECC_ST */ #define NFC_ECC_ERR(x) BIT(x) #define NFC_ECC_ERR_MSK GENMASK(15, 0) -#define NFC_ECC_PAT_FOUND(x) BIT(x + 16) + +/* + * define bit use in NFC_REG_PAT_FOUND + * For A10/A23, NFC_REG_PAT_FOUND =3D=3D NFC_ECC_ST register + */ +#define NFC_ECC_PAT_FOUND_MSK(nfc) (nfc->caps->pat_found_mask) + #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) =20 #define NFC_DEFAULT_TIMEOUT_MS 1000 @@ -216,6 +225,8 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_pat_found: Data Pattern Status Register + * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -225,6 +236,8 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_pat_found; + unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -766,7 +779,8 @@ static void sunxi_nfc_hw_ecc_update_stats(struct nand_c= hip *nand, } =20 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *= oob, - int step, u32 status, bool *erased) + int step, u32 status, u32 pattern_found, + bool *erased) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct nand_ecc_ctrl *ecc =3D &nand->ecc; @@ -777,7 +791,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, if (status & NFC_ECC_ERR(step)) return -EBADMSG; =20 - if (status & NFC_ECC_PAT_FOUND(step)) { + if (pattern_found & BIT(step)) { u8 pattern; =20 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) { @@ -811,6 +825,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int raw_mode =3D 0; + u32 pattern_found; bool erased; int ret; =20 @@ -838,8 +853,12 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chi= p *nand, =20 *cur_off =3D oob_off + ecc->bytes + 4; =20 + pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); + pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); + ret =3D sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, readl(nfc->regs + NFC_REG_ECC_ST), + pattern_found, &erased); if (erased) return 1; @@ -920,7 +939,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf unsigned int max_bitflips =3D 0; int ret, i, raw_mode =3D 0; struct scatterlist sg; - u32 status, wait; + u32 status, pattern_found, wait; =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -961,6 +980,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf return ret; =20 status =3D readl(nfc->regs + NFC_REG_ECC_ST); + pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); + pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); =20 for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; @@ -971,7 +992,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf =20 ret =3D sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL, oob_required ? oob : NULL, - i, status, &erased); + i, status, pattern_found, + &erased); =20 /* ECC errors are handled in the second loop. */ if (ret < 0) @@ -2185,6 +2207,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_found =3D NFC_REG_ECC_ST, + .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2195,6 +2219,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_found =3D NFC_REG_ECC_ST, + .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E68E9315D45 for ; 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charset="utf-8" The H6/H616 controller can't handle 512 bytes ecc block size. Let it be a capability. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 4cfb5d3e9c06..70c940840dda 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -222,6 +222,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. + * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register @@ -233,6 +234,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) */ struct sunxi_nfc_caps { bool has_mdma; + bool has_ecc_block_512; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; @@ -1748,8 +1750,14 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_c= hip *nand, sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION | NFC_ECC_PIPELINE | NFC_ECC_EN; =20 - if (ecc->size =3D=3D 512) - sunxi_nand->ecc.ecc_ctl |=3D NFC_ECC_BLOCK_512; + if (ecc->size =3D=3D 512) { + if (nfc->caps->has_ecc_block_512) { + sunxi_nand->ecc.ecc_ctl |=3D NFC_ECC_BLOCK_512; + } else { + dev_err(nfc->dev, "512B ECC block not supported\n"); + return -EOPNOTSUPP; + } + } =20 return 0; } @@ -2204,6 +2212,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { + .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, @@ -2216,6 +2225,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, + .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF3053164BB for ; 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charset="utf-8" The H6/H616 ECC_MODE field is not at the same offset, and has not the same size. So move the mask into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 70c940840dda..4118307cac15 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -29,8 +29,9 @@ #include #include =20 -/* non compile-time field get */ +/* non compile-time field get/prep */ #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) =20 #define NFC_REG_CTL 0x0000 #define NFC_REG_ST 0x0004 @@ -145,8 +146,8 @@ #define NFC_ECC_BLOCK_512 BIT(5) #define NFC_RANDOM_EN BIT(9) #define NFC_RANDOM_DIRECTION BIT(10) -#define NFC_ECC_MODE_MSK GENMASK(15, 12) -#define NFC_ECC_MODE(x) ((x) << 12) +#define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) +#define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) #define NFC_RANDOM_SEED(x) ((x) << 16) =20 @@ -227,6 +228,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register * @reg_pat_found: Data Pattern Status Register + * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array @@ -239,6 +241,7 @@ struct sunxi_nfc_caps { unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; unsigned int reg_pat_found; + unsigned int ecc_mode_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; @@ -1747,7 +1750,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, ecc->read_oob_raw =3D nand_read_oob_std; ecc->write_oob_raw =3D nand_write_oob_std; =20 - sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION | + sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(nfc, i) | NFC_ECC_EXCEPTION | NFC_ECC_PIPELINE | NFC_ECC_EN; =20 if (ecc->size =3D=3D 512) { @@ -2217,6 +2220,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, @@ -2230,6 +2234,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3D153164C6 for ; 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charset="utf-8" The H6/H616 RANDOM EN/DIRECTION masks are different from A10/A23. So move the masks into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 4118307cac15..3ccb7ea7cf17 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -144,8 +144,8 @@ #define NFC_ECC_EXCEPTION BIT(4) #define NFC_ECC_BLOCK_SIZE_MSK BIT(5) #define NFC_ECC_BLOCK_512 BIT(5) -#define NFC_RANDOM_EN BIT(9) -#define NFC_RANDOM_DIRECTION BIT(10) +#define NFC_RANDOM_EN(nfc) (nfc->caps->random_en_mask) +#define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) #define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) #define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) @@ -228,6 +228,8 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register * @reg_pat_found: Data Pattern Status Register + * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register + * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst @@ -241,6 +243,8 @@ struct sunxi_nfc_caps { unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; unsigned int reg_pat_found; + unsigned int random_en_mask; + unsigned int random_dir_mask; unsigned int ecc_mode_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; @@ -669,7 +673,7 @@ static void sunxi_nfc_randomizer_enable(struct nand_chi= p *nand) if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN, + writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN(nfc), nfc->regs + NFC_REG_ECC_CTL); } =20 @@ -680,7 +684,7 @@ static void sunxi_nfc_randomizer_disable(struct nand_ch= ip *nand) if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN, + writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN(nfc), nfc->regs + NFC_REG_ECC_CTL); } =20 @@ -2220,6 +2224,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .random_en_mask =3D BIT(9), + .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, @@ -2234,6 +2240,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .random_en_mask =3D BIT(9), + .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B4B26B742; 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charset="utf-8" The H6/H616 pattern ID register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 3ccb7ea7cf17..e8c08f0139d2 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -55,7 +55,8 @@ #define NFC_REG_A10_USER_DATA 0x0050 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 -#define NFC_REG_PAT_ID 0x00A4 +#define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) +#define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 #define NFC_REG_MDMA_CNT 0x00C4 #define NFC_RAM0_BASE 0x0400 @@ -227,6 +228,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register @@ -242,6 +244,7 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_pat_id; unsigned int reg_pat_found; unsigned int random_en_mask; unsigned int random_dir_mask; @@ -803,7 +806,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, if (pattern_found & BIT(step)) { u8 pattern; =20 - if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) { + if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID(nfc)) & 0x1))) { pattern =3D 0x0; } else { pattern =3D 0xff; @@ -2223,6 +2226,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), @@ -2239,6 +2243,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E92D2316902 for ; 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charset="utf-8" The H6/H616 spare area register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index e8c08f0139d2..da7b8b81d39e 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -54,7 +54,8 @@ #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) #define NFC_REG_A10_USER_DATA 0x0050 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) -#define NFC_REG_SPARE_AREA 0x00A0 +#define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) +#define NFC_REG_A10_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) #define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 @@ -228,6 +229,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_spare_area: Spare Area Register * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register @@ -244,6 +246,7 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_spare_area; unsigned int reg_pat_id; unsigned int reg_pat_found; unsigned int random_en_mask; @@ -466,7 +469,7 @@ static void sunxi_nfc_select_chip(struct nand_chip *nan= d, unsigned int cs) if (sel->rb >=3D 0) ctl |=3D NFC_RB_SEL(sel->rb); =20 - writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA(nfc)); =20 if (nfc->clk_rate !=3D sunxi_nand->clk_rate) { clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); @@ -2226,6 +2229,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_spare_area =3D NFC_REG_A10_SPARE_AREA, .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), @@ -2243,6 +2247,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_spare_area =3D NFC_REG_A10_SPARE_AREA, .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9351E3176E6 for ; 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charset="utf-8" The H6/H616 error mask register is bigger than the A10/A23 one, so move its mask into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index da7b8b81d39e..3de5642c05a8 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -155,7 +155,7 @@ =20 /* define bit use in NFC_ECC_ST */ #define NFC_ECC_ERR(x) BIT(x) -#define NFC_ECC_ERR_MSK GENMASK(15, 0) +#define NFC_ECC_ERR_MSK(nfc) (nfc->caps->ecc_err_mask) =20 /* * define bit use in NFC_REG_PAT_FOUND @@ -235,6 +235,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register + * @ecc_err_mask: NFC_ECC_ERR mask in NFC_ECC_ST register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array @@ -252,6 +253,7 @@ struct sunxi_nfc_caps { unsigned int random_en_mask; unsigned int random_dir_mask; unsigned int ecc_mode_mask; + unsigned int ecc_err_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; @@ -1030,7 +1032,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct na= nd_chip *nand, uint8_t *buf sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret); } =20 - if (status & NFC_ECC_ERR_MSK) { + if (status & NFC_ECC_ERR_MSK(nfc)) { for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; int oob_off =3D i * (ecc->bytes + 4); @@ -2235,6 +2237,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), + .ecc_err_mask =3D GENMASK(15, 0), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, @@ -2253,6 +2256,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), + .ecc_err_mask =3D GENMASK(15, 0), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E328317715 for ; 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charset="utf-8" The H6/H616 the SRAM is bigger than the A10/A23 one, so move its size into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 3de5642c05a8..e69fb0ac22b8 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -167,8 +167,6 @@ =20 #define NFC_DEFAULT_TIMEOUT_MS 1000 =20 -#define NFC_SRAM_SIZE 1024 - #define NFC_MAX_CS 7 =20 /** @@ -240,6 +238,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths + * @sram_size: Size of the NAND controller SRAM */ struct sunxi_nfc_caps { bool has_mdma; @@ -258,6 +257,7 @@ struct sunxi_nfc_caps { unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; + int sram_size; }; =20 /** @@ -495,7 +495,7 @@ static void sunxi_nfc_read_buf(struct nand_chip *nand, = uint8_t *buf, int len) while (len > offs) { bool poll =3D false; =20 - cnt =3D min(len - offs, NFC_SRAM_SIZE); + cnt =3D min(len - offs, nfc->caps->sram_size); =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -533,7 +533,7 @@ static void sunxi_nfc_write_buf(struct nand_chip *nand,= const uint8_t *buf, while (len > offs) { bool poll =3D false; =20 - cnt =3D min(len - offs, NFC_SRAM_SIZE); + cnt =3D min(len - offs, nfc->caps->sram_size); =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -1861,7 +1861,7 @@ static int sunxi_nfc_exec_subop(struct nand_chip *nan= d, case NAND_OP_DATA_OUT_INSTR: start =3D nand_subop_get_data_start_off(subop, i); remaining =3D nand_subop_get_data_len(subop, i); - cnt =3D min_t(u32, remaining, NFC_SRAM_SIZE); + cnt =3D min_t(u32, remaining, nfc->caps->sram_size); cmd |=3D NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; =20 if (instr->type =3D=3D NAND_OP_DATA_OUT_INSTR) { @@ -2242,6 +2242,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .sram_size =3D 1024, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { @@ -2261,6 +2262,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .sram_size =3D 1024, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BDC2318138 for ; Mon, 13 Oct 2025 15:28:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369284; cv=none; b=XryMzrsW0bU0bM+BKmkalBzOJTtatZA8wUhPPV9epMxLq2O2pCg2LVVw35VoNej4gHDbcovdABxy8yB8EWjRiw9XbBuXz8uMewS+C9Jek9+Wfsqny31O//xzLR9AHnY5Ki9y3HGIBYvxp0qq3CUC0L5w/jYwhYKt43EsPDFxFDE= ARC-Message-Signature: i=1; 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charset="utf-8" The H616 nand controller has the same base as A10/A23, with some differences: - mdma is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 190 ++++++++++++++++++++++++++++-- 1 file changed, 182 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index e69fb0ac22b8..29d17d4a0913 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -49,17 +49,40 @@ #define NFC_REG_A23_IO_DATA 0x0300 #define NFC_REG_ECC_CTL 0x0034 #define NFC_REG_ECC_ST 0x0038 -#define NFC_REG_DEBUG 0x003C +#define NFC_REG_H6_PAT_FOUND 0x003C #define NFC_REG_A10_ECC_ERR_CNT 0x0040 +#define NFC_REG_H6_ECC_ERR_CNT 0x0050 #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) +#define NFC_REG_H6_RDATA_CTL 0x0044 +#define NFC_REG_H6_RDATA_0 0x0048 +#define NFC_REG_H6_RDATA_1 0x004C #define NFC_REG_A10_USER_DATA 0x0050 +#define NFC_REG_H6_USER_DATA 0x0080 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) +#define NFC_REG_H6_USER_DATA_LEN 0x0070 +/* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */ +#define NFC_REG_USER_DATA_LEN_CAPACITY 8 +#define NFC_REG_USER_DATA_LEN(nfc, step) \ + (nfc->caps->reg_user_data_len + \ + ((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4) #define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) #define NFC_REG_A10_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) #define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 #define NFC_REG_MDMA_CNT 0x00C4 +#define NFC_REG_H6_EFNAND_STATUS 0x0110 +#define NFC_REG_H6_SPARE_AREA 0x0114 +#define NFC_REG_H6_PAT_ID 0x0118 +#define NFC_REG_H6_DDR2_SPEC_CTL 0x011C +#define NFC_REG_H6_NDMA_MODE_CTL 0x0120 +#define NFC_REG_H6_MDMA_DLBA_REG 0x0200 +#define NFC_REG_H6_MDMA_STA 0x0204 +#define NFC_REG_H6_MDMA_INT_MAS 0x0208 +#define NFC_REG_H6_MDMA_DESC_ADDR 0x020C +#define NFC_REG_H6_MDMA_BUF_ADDR 0x0210 +#define NFC_REG_H6_MDMA_CNT 0x0214 + #define NFC_RAM0_BASE 0x0400 #define NFC_RAM1_BASE 0x0800 =20 @@ -71,6 +94,7 @@ #define NFC_BUS_WIDTH_16 (1 << 2) #define NFC_RB_SEL_MSK BIT(3) #define NFC_RB_SEL(x) ((x) << 3) +/* CE_SEL BIT 27 is meant to be used for GPIO chipselect */ #define NFC_CE_SEL_MSK GENMASK(26, 24) #define NFC_CE_SEL(x) ((x) << 24) #define NFC_CE_CTL BIT(6) @@ -89,6 +113,9 @@ #define NFC_STA BIT(4) #define NFC_NATCH_INT_FLAG BIT(5) #define NFC_RB_STATE(x) BIT(x + 8) +#define NFC_RB_STATE_MSK GENMASK(11, 8) +#define NDFC_RDATA_STA_1 BIT(12) +#define NDFC_RDATA_STA_0 BIT(13) =20 /* define bit use in NFC_INT */ #define NFC_B2R_INT_ENABLE BIT(0) @@ -100,6 +127,7 @@ =20 /* define bit use in NFC_TIMING_CTL */ #define NFC_TIMING_CTL_EDO BIT(8) +#define NFC_TIMING_CTL_E_EDO BIT(9) =20 /* define NFC_TIMING_CFG register layout */ #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ @@ -107,9 +135,15 @@ (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ (((tCAD) & 0x7) << 8)) =20 +#define NFC_TIMING_CFG2(tCDQSS, tSC, tCLHZ, tCSS, tWC) \ + ((((tCDQSS) & 0x1) << 11) | (((tSC) & 0x3) << 12) | \ + (((tCLHZ) & 0x3) << 14) | (((tCSS) & 0x3) << 16) | \ + (((tWC) & 0x3) << 18)) + /* define bit use in NFC_CMD */ #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0) -#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) +#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) // 15-10 reserved on H6 +#define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8) #define NFC_CMD(x) (x) #define NFC_ADR_NUM_MSK GENMASK(18, 16) #define NFC_ADR_NUM(x) (((x) - 1) << 16) @@ -122,6 +156,7 @@ #define NFC_SEQ BIT(25) #define NFC_DATA_SWAP_METHOD BIT(26) #define NFC_ROW_AUTO_INC BIT(27) +#define NFC_H6_SEND_RND_CMD2 BIT(27) #define NFC_SEND_CMD3 BIT(28) #define NFC_SEND_CMD4 BIT(29) #define NFC_CMD_TYPE_MSK GENMASK(31, 30) @@ -133,6 +168,7 @@ #define NFC_READ_CMD_MSK GENMASK(7, 0) #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8) #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16) +#define NFC_RND_READ_CMD2_MSK GENMASK(31, 24) =20 /* define bit use in NFC_WCMD_SET */ #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0) @@ -150,6 +186,9 @@ #define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) #define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) #define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) +/* RANDOM_PAGE_SIZE: 0: ECC block size 1: page size */ +#define NFC_A23_RANDOM_PAGE_SIZE BIT(11) +#define NFC_H6_RANDOM_PAGE_SIZE BIT(7) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) #define NFC_RANDOM_SEED(x) ((x) << 16) =20 @@ -165,6 +204,9 @@ =20 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) =20 +#define NFC_USER_DATA_LEN_MSK(step) \ + (0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4)) + #define NFC_DEFAULT_TIMEOUT_MS 1000 =20 #define NFC_MAX_CS 7 @@ -224,9 +266,12 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(st= ruct nand_chip *nand) * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks + * @has_ecc_clk: If the controller needs an ECC clock. + * @has_mbus_clk: If the controller needs a mbus clock. * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_user_data_len: User data length register * @reg_spare_area: Spare Area Register * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register @@ -238,14 +283,24 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(s= truct nand_chip *nand) * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths + * @max_ecc_steps: Maximum supported steps for ECC, this is also the + * number of user data registers + * @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN regist= er + * The table index is the value to set in NFC_USER_DATA_LEN + * registers, and the corresponding value is the number of + * bytes to write + * @nuser_data_tab: Size of @user_data_len_tab * @sram_size: Size of the NAND controller SRAM */ struct sunxi_nfc_caps { bool has_mdma; bool has_ecc_block_512; + bool has_ecc_clk; + bool has_mbus_clk; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_user_data_len; unsigned int reg_spare_area; unsigned int reg_pat_id; unsigned int reg_pat_found; @@ -257,6 +312,9 @@ struct sunxi_nfc_caps { unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; + const u8 *user_data_len_tab; + unsigned int nuser_data_tab; + unsigned int max_ecc_steps; int sram_size; }; =20 @@ -268,6 +326,8 @@ struct sunxi_nfc_caps { * @regs: NAND controller registers * @ahb_clk: NAND controller AHB clock * @mod_clk: NAND controller mod clock + * @ecc_clk: NAND controller ECC clock + * @mbus_clk: NAND controller MBUS clock * @reset: NAND controller reset line * @assigned_cs: bitmask describing already assigned CS lines * @clk_rate: NAND controller current clock rate @@ -283,6 +343,8 @@ struct sunxi_nfc { void __iomem *regs; struct clk *ahb_clk; struct clk *mod_clk; + struct clk *ecc_clk; + struct clk *mbus_clk; struct reset_control *reset; unsigned long assigned_cs; unsigned long clk_rate; @@ -764,6 +826,53 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct= nand_chip *nand, u8 *oob, sunxi_nfc_randomize_bbm(nand, page, oob); } =20 +/* + * On H6/H6 the user_data length has to be set in specific registers + * before writing. + */ +static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc) +{ + int loop_step =3D NFC_REG_USER_DATA_LEN_CAPACITY; + + /* not all SoCs have this register */ + if (!nfc->caps->reg_user_data_len) + return; + + for (int i =3D 0; i < nfc->caps->max_ecc_steps; i +=3D loop_step) + writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i)); +} + +static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc, + int len, int step) +{ + bool found =3D false; + u32 val; + int i; + + /* not all SoCs have this register */ + if (!nfc->caps->reg_user_data_len) + return; + + for (i =3D 0; i < nfc->caps->nuser_data_tab; i++) { + if (len =3D=3D nfc->caps->user_data_len_tab[i]) { + found =3D true; + break; + } + } + + if (!found) { + dev_warn(nfc->dev, + "Unsupported length for user data reg: %d\n", len); + return; + } + + val =3D readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); + + val &=3D ~NFC_USER_DATA_LEN_MSK(step); + val |=3D field_prep(NFC_USER_DATA_LEN_MSK(step), i); + writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); +} + static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand, const u8 *oob, int step, bool bbm, int page) @@ -858,6 +967,8 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, if (ret) return ret; =20 + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, 4, 0); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, @@ -968,6 +1079,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nan= d_chip *nand, uint8_t *buf return ret; =20 sunxi_nfc_hw_ecc_enable(nand); + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, 4, 0); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); =20 @@ -1100,6 +1213,8 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, =20 sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, 4, 0); sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page); =20 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | @@ -1344,10 +1459,12 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct n= and_chip *nand, if (ret) goto pio_fallback; =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D 0; i < ecc->steps; i++) { const u8 *oob =3D nand->oob_poi + (i * (ecc->bytes + 4)); =20 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); + sunxi_nfc_set_user_data_len(nfc, 4, i); } =20 nand_prog_page_begin_op(nand, page, 0, NULL, 0); @@ -2148,6 +2265,10 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) if (irq < 0) return irq; =20 + nfc->caps =3D of_device_get_match_data(dev); + if (!nfc->caps) + return -EINVAL; + nfc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); if (IS_ERR(nfc->ahb_clk)) { dev_err(dev, "failed to retrieve ahb clk\n"); @@ -2160,6 +2281,22 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) return PTR_ERR(nfc->mod_clk); } =20 + if (nfc->caps->has_ecc_clk) { + nfc->ecc_clk =3D devm_clk_get_enabled(dev, "ecc"); + if (IS_ERR(nfc->ecc_clk)) { + dev_err(dev, "failed to retrieve ecc clk\n"); + return PTR_ERR(nfc->ecc_clk); + } + } + + if (nfc->caps->has_mbus_clk) { + nfc->mbus_clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(nfc->mbus_clk)) { + dev_err(dev, "failed to retrieve mbus clk\n"); + return PTR_ERR(nfc->mbus_clk); + } + } + nfc->reset =3D devm_reset_control_get_optional_exclusive(dev, "ahb"); if (IS_ERR(nfc->reset)) return PTR_ERR(nfc->reset); @@ -2170,12 +2307,6 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) return ret; } =20 - nfc->caps =3D of_device_get_match_data(&pdev->dev); - if (!nfc->caps) { - ret =3D -EINVAL; - goto out_ahb_reset_reassert; - } - ret =3D sunxi_nfc_rst(nfc); if (ret) goto out_ahb_reset_reassert; @@ -2226,8 +2357,18 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; =20 +static const u8 sunxi_ecc_strengths_h6[] =3D { + 16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 +}; + +static const u8 sunxi_user_data_len_h6[] =3D { + 0, 4, 8, 12, 16, 20, 24, 28, 32 +}; + static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .has_ecc_block_512 =3D true, + .has_ecc_clk =3D false, + .has_mbus_clk =3D false, .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, @@ -2242,11 +2383,14 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_ca= ps =3D { .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .max_ecc_steps =3D 16, .sram_size =3D 1024, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, + .has_ecc_clk =3D false, + .has_mbus_clk =3D false, .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, @@ -2262,9 +2406,35 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_cap= s =3D { .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .max_ecc_steps =3D 16, .sram_size =3D 1024, }; =20 +static const struct sunxi_nfc_caps sunxi_nfc_h616_caps =3D { + .has_mdma =3D false, // H616 supports only chained descriptors + .has_ecc_clk =3D true, + .has_mbus_clk =3D true, + .reg_io_data =3D NFC_REG_A23_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_H6_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_H6_USER_DATA, + .reg_user_data_len =3D NFC_REG_H6_USER_DATA_LEN, + .reg_spare_area =3D NFC_REG_H6_SPARE_AREA, + .reg_pat_id =3D NFC_REG_H6_PAT_ID, + .reg_pat_found =3D NFC_REG_H6_PAT_FOUND, + .random_en_mask =3D BIT(5), + .random_dir_mask =3D BIT(6), + .ecc_mode_mask =3D GENMASK(15, 8), + .ecc_err_mask =3D GENMASK(31, 0), + .pat_found_mask =3D GENMASK(31, 0), + .dma_maxburst =3D 8, + .ecc_strengths =3D sunxi_ecc_strengths_h6, + .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_h6), + .user_data_len_tab =3D sunxi_user_data_len_h6, + .nuser_data_tab =3D ARRAY_SIZE(sunxi_user_data_len_h6), + .max_ecc_steps =3D 32, + .sram_size =3D 8192, +}; + static const struct of_device_id sunxi_nfc_ids[] =3D { { .compatible =3D "allwinner,sun4i-a10-nand", @@ -2274,6 +2444,10 @@ static const struct of_device_id sunxi_nfc_ids[] =3D= { .compatible =3D "allwinner,sun8i-a23-nand-controller", .data =3D &sunxi_nfc_a23_caps, }, + { + .compatible =3D "allwinner,sun50i-h616-nand-controller", + .data =3D &sunxi_nfc_h616_caps, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sunxi_nfc_ids); From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9DC13191A3 for ; Mon, 13 Oct 2025 15:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369286; cv=none; b=nbzeB9RNIDegoq+GHKFRMmFW8LsaJ9pyXDAIBqqXgG6HIvaqIRXQ76TeIU+UVLEqXV0WbXyDAW0F4DkbPcbYxZUFkFjtYBugtedGylmpQq7bKMRtheEUDqIQXH1EJxjmRXimMTLQP4JBILzFKCcL+zHabSnnTzfvALmf0OOf7X8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760369286; c=relaxed/simple; bh=LPpFGckQlGu41PWKhM1jFADnk8iS1JnOVJ7LQRpoM1U=; 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Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 14/15] dt-bindings: mtd: sunxi: Add H616 compatible Date: Mon, 13 Oct 2025 17:26:44 +0200 Message-ID: <20251013152645.1119308-15-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 NAND controller is quite different from the A10 and A23 ones, some registers offset changed, and some new one are introduced. Also, the DMA handling is different (it uses chained descriptors) So, introduce a new compatible to represent this version of the IP. Signed-off-by: Richard Genoud --- .../mtd/allwinner,sun4i-a10-nand.yaml | 57 ++++++++++++++++--- 1 file changed, 48 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand= .yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml index 054b6b8bf9b9..4b82de9fae17 100644 --- a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Allwinner A10 NAND Controller =20 -allOf: - - $ref: nand-controller.yaml - maintainers: - Chen-Yu Tsai - Maxime Ripard @@ -18,6 +15,8 @@ properties: enum: - allwinner,sun4i-a10-nand - allwinner,sun8i-a23-nand-controller + - allwinner,sun50i-h616-nand-controller + reg: maxItems: 1 =20 @@ -25,14 +24,12 @@ properties: maxItems: 1 =20 clocks: - items: - - description: Bus Clock - - description: Module Clock + minItems: 2 + maxItems: 4 =20 clock-names: - items: - - const: ahb - - const: mod + minItems: 2 + maxItems: 4 =20 resets: maxItems: 1 @@ -85,6 +82,48 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-nand + - allwinner,sun8i-a23-nand-controller + then: + properties: + clocks: + items: + - description: Bus Clock + - description: Module Clock + clock-names: + items: + - const: ahb + - const: mod + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-nand-controller + then: + properties: + clocks: + items: + - description: Bus Clock + - description: Module Clock + - description: ECC Clock + - description: MBus Clock + clock-names: + items: + - const: ahb + - const: mod + - const: ecc + - const: mbus + examples: - | #include From nobody Fri Dec 19 15:30:05 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EA563191C4 for ; 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bh=DH7a2TSjC2EHRtCltLIXQ56Gx/zxJGstZzcrhDDVRTc=; b=vm4q6bOOFq44I9xd7zWEfS4NDHsjVzBwyWgLd1oaepsy9fQ1gnZ86zupCQCfUs2GePKDPo 9W12689n6cTZH9S5zOdzCicGXXah0xzp5z7ny+hwz0NvtBXzDUJx6CJ0xcjeUyPpwKSHHl yALkEOIThvFKahA/LehQEPX5AcjcTmRZyULPkA9X1H7knPqMu14iJXpDOaJa1LJW1WEoB6 niAW8NSmxpCvtydMC/d+wTFFwqPDzP4bbo4PLt9lrGgFFXTXTkgcrGXhimSlnoMSEWXS6d tFJ/cJCeXzB3GGR63ubM+XSSJdNSSjD6RGrIs35BFn5ZJMYcP2nI0/9JFMxqLw== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller Date: Mon, 13 Oct 2025 17:26:45 +0200 Message-ID: <20251013152645.1119308-16-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 has a NAND controller quite similar to the A10/A23 ones, but with some register differences, more clocks (for ECC and MBUS), more ECC strengths, so this requires a new compatible string. Add the NAND controller node and pins in the device tree. Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index ceedae9e399b..bb53c6c63836 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + /omit-if-no-ref/ + nand_pins: nand-pins { + pins =3D "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function =3D "nand0"; + }; + + /omit-if-no-ref/ + nand_cs0_pin: nand-cs0-pin { + pins =3D "PC4"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_cs1_pin: nand-cs1-pin { + pins =3D "PC3"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb0_pin: nand-rb0-pin { + pins =3D "PC6"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb1_pin: nand-rb1-pin { + pins =3D "PC7"; + function =3D "nand0"; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins =3D "PC0", "PC2", "PC4"; @@ -377,6 +413,21 @@ iommu: iommu@30f0000 { #iommu-cells =3D <1>; }; =20 + nfc: nand-controller@4011000 { + compatible =3D "allwinner,sun50i-h616-nand-controller"; + reg =3D <0x04011000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; + clock-names =3D "ahb", "mod", "ecc", "mbus"; + resets =3D <&ccu RST_BUS_NAND>; + reset-names =3D "ahb"; + dmas =3D <&dma 10>; + dma-names =3D "rxtx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + mmc0: mmc@4020000 { compatible =3D "allwinner,sun50i-h616-mmc", "allwinner,sun50i-a100-mmc";