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charset="utf-8" Add edp reference clock for sa8775p edp phy. Signed-off-by: Ritesh Kumar --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index bfc4d75f50ff..b0e4015596de 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -73,6 +73,7 @@ allOf: compatible: enum: - qcom,x1e80100-dp-phy + - qcom,sa8775p-edp-phy then: properties: clocks: --=20 2.17.1 From nobody Sun Feb 8 23:13:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C9C930496A; Mon, 13 Oct 2025 10:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Update clock entry in edp phy example node to add support for edp reference clock. Signed-off-by: Ritesh Kumar --- .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index e2730a2f25cf..16bb3f7043c8 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -200,9 +200,11 @@ examples: <0x0aec2000 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; --=20 2.17.1 From nobody Sun Feb 8 23:13:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7648D303A12; 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charset="utf-8" Add edp reference clock for edp phy on lemans chipset. Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index cf685cb186ed..1bcf1edd9382 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5034,9 +5034,11 @@ <0x0 0x0aec2000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; @@ -5053,9 +5055,11 @@ <0x0 0x0aec5000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; --=20 2.17.1