From nobody Mon Feb 9 07:21:00 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 791302FE05B for ; Mon, 13 Oct 2025 10:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352150; cv=none; b=bAEWarXDp3jG+eiremFne2AS9UAnwVnRnv6wmtUT9QPAlc9rzan1umyrC66ArFthclOFXvDKaT32pAwuc0te+eEGdHLOz8IXlR1/0HmimdK9cYKTF+hgPMzRpcoxsNWDaZMDDv0SR7zD0PL9tuBUuvKmeqHv8DhKtqPkJzJQG/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352150; c=relaxed/simple; bh=5kDBCsrNHD+lfYpSaurI9bABB4ZUqKNpN1zxDJ8qQIU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OCuuYvM7oWlM6e4ZKJdxpYuexwGvvYPOayJ7HfBONQcrKMCg250sYLFBt4pRbPnxW06KAMHyGc/wcl4LuHl2MWZvFVL41F4DiPOdCorb6XZw+kK1OcxtCVCdq0DXXS7YraNgEBXAGXeAwyf2pJh7a9aFUPxrSs5/nMM1WKOnbUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg63V075209 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:06 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:06 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver Date: Mon, 13 Oct 2025 18:41:42 +0800 Message-ID: <20251013104146.578319-2-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg63V075209 Content-Type: text/plain; charset="utf-8" The number of ob/ib windows is determined through write-read loops on registers in the core driver. Some glue drivers need to adjust the number of ob/ib windows to meet specific requirements,such as hardware limitations. This change allows the glue driver to adjust the number of ob/ib windows to satisfy platform-specific constraints. The glue driver may adjust the number of ob/ib windows, but the values must stay within hardware limits. Signed-off-by: Randolph Lin --- drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c644216995f6..a860890febc3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -851,8 +851,16 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) max =3D 0; } =20 - pci->num_ob_windows =3D ob; - pci->num_ib_windows =3D ib; + if (!pci->num_ob_windows) + pci->num_ob_windows =3D ob; + else if (pci->num_ob_windows > ob) + dev_err(pci->dev, "Adjusted ob windows exceed the limit\n"); + + if (!pci->num_ib_windows) + pci->num_ib_windows =3D ib; + else if (pci->num_ib_windows > ib) + dev_err(pci->dev, "Adjusted ib windows exceed the limit\n"); + pci->region_align =3D 1 << fls(min); pci->region_limit =3D (max << 32) | (SZ_4G - 1); =20 --=20 2.34.1