From nobody Sat Feb 7 19:45:31 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 791302FE05B for ; Mon, 13 Oct 2025 10:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352150; cv=none; b=bAEWarXDp3jG+eiremFne2AS9UAnwVnRnv6wmtUT9QPAlc9rzan1umyrC66ArFthclOFXvDKaT32pAwuc0te+eEGdHLOz8IXlR1/0HmimdK9cYKTF+hgPMzRpcoxsNWDaZMDDv0SR7zD0PL9tuBUuvKmeqHv8DhKtqPkJzJQG/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352150; c=relaxed/simple; bh=5kDBCsrNHD+lfYpSaurI9bABB4ZUqKNpN1zxDJ8qQIU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OCuuYvM7oWlM6e4ZKJdxpYuexwGvvYPOayJ7HfBONQcrKMCg250sYLFBt4pRbPnxW06KAMHyGc/wcl4LuHl2MWZvFVL41F4DiPOdCorb6XZw+kK1OcxtCVCdq0DXXS7YraNgEBXAGXeAwyf2pJh7a9aFUPxrSs5/nMM1WKOnbUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg63V075209 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:06 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:06 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver Date: Mon, 13 Oct 2025 18:41:42 +0800 Message-ID: <20251013104146.578319-2-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg63V075209 Content-Type: text/plain; charset="utf-8" The number of ob/ib windows is determined through write-read loops on registers in the core driver. Some glue drivers need to adjust the number of ob/ib windows to meet specific requirements,such as hardware limitations. This change allows the glue driver to adjust the number of ob/ib windows to satisfy platform-specific constraints. The glue driver may adjust the number of ob/ib windows, but the values must stay within hardware limits. Signed-off-by: Randolph Lin --- drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c644216995f6..a860890febc3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -851,8 +851,16 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) max =3D 0; } =20 - pci->num_ob_windows =3D ob; - pci->num_ib_windows =3D ib; + if (!pci->num_ob_windows) + pci->num_ob_windows =3D ob; + else if (pci->num_ob_windows > ob) + dev_err(pci->dev, "Adjusted ob windows exceed the limit\n"); + + if (!pci->num_ib_windows) + pci->num_ib_windows =3D ib; + else if (pci->num_ib_windows > ib) + dev_err(pci->dev, "Adjusted ib windows exceed the limit\n"); + pci->region_align =3D 1 << fls(min); pci->region_limit =3D (max << 32) | (SZ_4G - 1); =20 --=20 2.34.1 From nobody Sat Feb 7 19:45:31 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 790B92FB99E for ; Mon, 13 Oct 2025 10:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352163; cv=none; b=XiP+xac2ikNHq8YZ8ySG2Jc9xVCVhiPiB0ZtPKA3U+R9QGu+M06jJ2LQQaOJEs/WQQ94tWIdyWbsa+p9FoNMoJu7H6SAD78JT0gomjYzk3ayGCNE3BFZT142By6RnvHuXj/9fGqR9niqcw64ROn8WqXz75W4/J9UxhXo/JH/UUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352163; c=relaxed/simple; bh=+PcykRvZ8BhBNKZfMa/Q65wJi1W62px+VbpGfwiqP0U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qNVZV3fvFX9wkAZpSF9mqvGV4rKXSJ2B5RaApEGRkxLRiBXJ8kbkmffmlcxyH36TTo2SfpdKlKkU1hOZVqW1k19IvdXdWwpI7BegJohybJYt1mIZI/BjmosGXiOjmB5cAR7DGyVVGBMo0poyMYOeRQvwi3bxmalS2/9zaTda8Hw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=unknown smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=tempfail smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg7R4075217 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:07 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:07 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support Date: Mon, 13 Oct 2025 18:41:43 +0800 Message-ID: <20251013104146.578319-3-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg7R4075217 Content-Type: text/plain; charset="utf-8" Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Only one example is required in the DTS bindings YAML file. Signed-off-by: Randolph Lin --- .../bindings/pci/andestech,qilai-pcie.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-p= cie.yaml diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yam= l b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml new file mode 100644 index 000000000000..ca444e4766ec --- /dev/null +++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes QiLai PCIe host controller + +description: + Andes QiLai PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +maintainers: + - Randolph Lin + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: andestech,qilai-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: APB registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: apb + - const: config + + ranges: + maxItems: 2 + + interrupts: + maxItems: 1 + +required: + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@80000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x0 0x80000000 0x0 0x20000000>, + <0x0 0x04000000 0x0 0x00001000>, + <0x0 0x00000000 0x0 0x00010000>; + reg-names =3D "dbi", "apb", "config"; + + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000= 000>, + <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x0000000= 0>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xf>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic0>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... --=20 2.34.1 From nobody Sat Feb 7 19:45:31 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E3512FF147 for ; Mon, 13 Oct 2025 10:42:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352165; cv=none; b=hfQ8NcLE/erUQJzAG5fQpQERuyqnF3krUD1fKJRKW+ozMbkCfecoajhdCayqoNJ2EFhbtEuS0+oJ4smMn10Kw/KgQ1orYQMiK/mlrKuBPpxCIeENS7zooX17ar1mgaG0NhbA8GU+wKgeu3YIAU26JrbXDqwmL3WTe0rB+xlN07s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760352165; c=relaxed/simple; bh=LKggEBidnDaoYAZy2tX0K+iAOnLSLC3Hm2DoyOcDOqc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MO8Epz9JfpKKQ/PYei1c/xPqboSbyLJmI+7hiO9WIcf0qlTkknYdjP+v/xndydrptiNX0drh5LQjQg9dQ4VkqKHlHBP4eRJL96A6xeTlxwgpF1uvmqDZRgkzsMuIL6WK8oYS13pfsfYOCNKqy8plUjHpWbKifkSZJ7KaZB03Az0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg7qM075222 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:07 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:07 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Date: Mon, 13 Oct 2025 18:41:44 +0800 Message-ID: <20251013104146.578319-4-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg7qM075222 Content-Type: text/plain; charset="utf-8" Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Signed-off-by: Randolph Lin --- arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi index de3de32f8c39..afa7b75a7e7a 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -182,5 +182,111 @@ uart0: serial@30300000 { reg-io-width =3D <4>; no-loopback-test; }; + + bus@80000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>, + <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>, + <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>; + + pcie@80000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04000000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000= >, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xf 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xf 0x4>, + <0 0 0 2 &plic 0xf 0x4>, + <0 0 0 3 &plic 0xf 0x4>, + <0 0 0 4 &plic 0xf 0x4>; + }; + }; + + bus@a0000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>, + <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>, + <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>; + + pcie@a0000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04001000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xe 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xe 0x4>, + <0 0 0 2 &plic 0xe 0x4>, + <0 0 0 3 &plic 0xe 0x4>, + <0 0 0 4 &plic 0xe 0x4>; + }; + }; + + bus@c0000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>, + <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>, + <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>; + + pcie@c0000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04002000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + linux,pci-domain =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xd 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xd 0x4>, + <0 0 0 2 &plic 0xd 0x4>, + <0 0 0 3 &plic 0xd 0x4>, + <0 0 0 4 &plic 0xd 0x4>; + }; + }; + }; }; --=20 2.34.1 From nobody Sat Feb 7 19:45:31 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 744F82FF163 for ; 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dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=tempfail smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg8mM075223 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:08 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:08 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support Date: Mon, 13 Oct 2025 18:41:45 +0800 Message-ID: <20251013104146.578319-5-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg8mM075223 Content-Type: text/plain; charset="utf-8" Add driver support for DesignWare based PCIe controller in Andes QiLai SoC. The driver only supports the Root Complex mode. Signed-off-by: Randolph Lin --- drivers/pci/controller/dwc/Kconfig | 13 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-andes-qilai.c | 240 ++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 349d4657393c..09ce40640e2f 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -61,6 +61,19 @@ config PCI_MESON and therefore the driver re-uses the DesignWare core functions to implement the driver. =20 +config PCIE_ANDES_QILAI + tristate "Andes QiLai PCIe controller" + depends on ARCH_ANDES || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Say Y here to enable PCIe controller support on Andes QiLai SoCs, + which operate in Root Complex mode. The Andes QiLai SoC PCIe + controller is based on DesignWare IP (5.97a version) and therefore + the driver re-uses the DesignWare core functions to implement the + driver. The Andes QiLai SoC features three Root Complexes, each + operating on PCIe 4.0. + config PCIE_ARTPEC6 bool =20 diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 7ae28f3b0fb3..5d3ec2d26275 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) +=3D pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o obj-$(CONFIG_PCIE_AMD_MDB) +=3D pcie-amd-mdb.o +obj-$(CONFIG_PCIE_ANDES_QILAI) +=3D pcie-andes-qilai.o obj-$(CONFIG_PCIE_BT1) +=3D pcie-bt1.o obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/co= ntroller/dwc/pcie-andes-qilai.c new file mode 100644 index 000000000000..fd1521a5e89c --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the PCIe Controller in QiLai from Andes + * + * Copyright (C) 2025 Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define PCIE_INTR_CONTROL1 0x15c +#define PCIE_MSI_CTRL_INT_EN BIT(28) + +#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8 + +/* + * Refer to Table A4-5 (Memory type encoding) in the + * AMBA AXI and ACE Protocol Specification. + * + * The selected value corresponds to the Memory type field: + * "Write-back, Read and Write-allocate". + * + * The last three rows in the table A4-5 in + * AMBA AXI and ACE Protocol Specification: + * ARCACHE AWCACHE Memory type + * ------------------------------------------------------------------ + * 1111 (0111) 0111 Write-back Read-allocate + * 1011 1111 (1011) Write-back Write-allocate + * 1111 1111 Write-back Read and Write-allocate (selec= ted) + */ +#define IOCP_ARCACHE 0b1111 +#define IOCP_AWCACHE 0b1111 + +#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3) +#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11) +#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19) +#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27) + +#define PCIE_GEN_CONTROL2 0x54 +#define PCIE_CFG_LTSSM_EN BIT(0) + +#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0 +#define SMLH_LINK_UP BIT(6) +#define RDLH_LINK_UP BIT(7) +#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP) + +struct qilai_pcie { + struct dw_pcie pci; + void __iomem *apb_base; +}; + +#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci) + +static bool qilai_pcie_link_up(struct dw_pcie *pci) +{ + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + u32 val; + + /* Read smlh & rdlh link up by checking debug port */ + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); + + return (val & PCIE_REGS_PCIE_SII_LINK_UP) =3D=3D PCIE_REGS_PCIE_SII_LINK_= UP; +} + +static int qilai_pcie_start_link(struct dw_pcie *pci) +{ + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + u32 val; + + val =3D readl(pcie->apb_base + PCIE_GEN_CONTROL2); + val |=3D PCIE_CFG_LTSSM_EN; + writel(val, pcie->apb_base + PCIE_GEN_CONTROL2); + + return 0; +} + +static const struct dw_pcie_ops qilai_pcie_ops =3D { + .link_up =3D qilai_pcie_link_up, + .start_link =3D qilai_pcie_start_link, +}; + +/* + * Setup the Qilai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to t= he + * Write-Back, Read and Write Allocate mode. + * + * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as = the + * system cache. The IOCP HW helps maintain cache monitoring, ensuring that + * the device can snoop data from/to the cache. + */ +static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3, + sizeof(val), &val); + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE); + dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3, + sizeof(val), val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + +static void qilai_pcie_enable_msi(struct qilai_pcie *pcie) +{ + u32 val; + + val =3D readl(pcie->apb_base + PCIE_INTR_CONTROL1); + val |=3D PCIE_MSI_CTRL_INT_EN; + writel(val, pcie->apb_base + PCIE_INTR_CONTROL1); +} + +/* + * The QiLai SoC PCIe controller's outbound iATU region supports + * a maximum size of SZ_4G - 1. To prevent programming failures, + * only consider bridge->windows with sizes within this limit. + * + * To ensure compatibility with most endpoint devices, at least + * one memory region must be mapped within the 32-bits address space. + */ +static int qilai_pcie_host_fix_ob_iatu_count(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct device *dev =3D pci->dev; + struct resource_entry *entry; + /* Reserved 1 ob iATU for config space */ + int count =3D 1; + int ranges_32bits; + u64 pci_addr; + u64 size; + + resource_list_for_each_entry(entry, &pp->bridge->windows) { + if (resource_type(entry->res) !=3D IORESOURCE_MEM) + continue; + + size =3D resource_size(entry->res); + if (size < SZ_4G) + count++; + + pci_addr =3D entry->res->start - entry->offset; + if (pci_addr < SZ_4G) + ranges_32bits =3D true; + } + + if (!ranges_32bits) { + dev_err(dev, "Bridge window must contain 32-bits address\n"); + return -EINVAL; + } + + pci->num_ob_windows =3D count; + + return 0; +} + +static int qilai_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + + qilai_pcie_enable_msi(pcie); + + return qilai_pcie_host_fix_ob_iatu_count(pp); +} + +static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp) +{ + qilai_pcie_iocp_cache_setup(pp); +} + +static const struct dw_pcie_host_ops qilai_pcie_host_ops =3D { + .init =3D qilai_pcie_host_init, + .post_init =3D qilai_pcie_host_post_init, +}; + +static int qilai_pcie_probe(struct platform_device *pdev) +{ + struct qilai_pcie *pcie; + struct dw_pcie *pci; + struct device *dev =3D &pdev->dev; + int ret; + + pcie =3D devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + platform_set_drvdata(pdev, pcie); + + pci =3D &pcie->pci; + pcie->pci.dev =3D dev; + pcie->pci.ops =3D &qilai_pcie_ops; + pcie->pci.pp.ops =3D &qilai_pcie_host_ops; + pci->use_parent_dt_ranges =3D true; + + dw_pcie_cap_set(&pcie->pci, REQ_RES); + + pcie->apb_base =3D devm_platform_ioremap_resource_byname(pdev, "apb"); + if (IS_ERR(pcie->apb_base)) + return PTR_ERR(pcie->apb_base); + + ret =3D dw_pcie_host_init(&pcie->pci.pp); + if (ret) { + dev_err_probe(dev, ret, "Failed to initialize PCIe host\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id qilai_pcie_of_match[] =3D { + { .compatible =3D "andestech,qilai-pcie" }, + {}, +}; +MODULE_DEVICE_TABLE(of, qilai_pcie_of_match); + +static struct platform_driver qilai_pcie_driver =3D { + .probe =3D qilai_pcie_probe, + .driver =3D { + .name =3D "qilai-pcie", + .of_match_table =3D qilai_pcie_of_match, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +builtin_platform_driver(qilai_pcie_driver); + +MODULE_AUTHOR("Randolph Lin "); +MODULE_DESCRIPTION("Andes Qilai PCIe driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sat Feb 7 19:45:31 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646FD2FF67F for ; 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dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59DAg8CS075224 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Oct 2025 18:42:08 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Oct 2025 18:42:08 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v7 5/5] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Date: Mon, 13 Oct 2025 18:41:46 +0800 Message-ID: <20251013104146.578319-6-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251013104146.578319-1-randolph@andestech.com> References: <20251013104146.578319-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59DAg8CS075224 Content-Type: text/plain; charset="utf-8" Here add maintainer information for Andes QiLai PCIe driver. Signed-off-by: Randolph Lin --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..fb1d4daafe44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19591,6 +19591,13 @@ S: Supported F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml F: drivers/pci/controller/pcie-altera.c =20 +PCI DRIVER FOR ANDES QILAI PCIE +M: Randolph Lin +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml +F: drivers/pci/controller/dwc/pcie-andes-qilai.c + PCI DRIVER FOR APPLIEDMICRO XGENE M: Toan Le L: linux-pci@vger.kernel.org --=20 2.34.1