From nobody Wed Dec 17 07:40:02 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8624C2DF138; Mon, 13 Oct 2025 06:31:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760337120; cv=none; b=LF32Tvqzx6hHMQQz5VdwXcFY8VsWT+OWmRq1gGalFQi2+wAhW1yO6aHPnAAEqceDuDu4bqsP4IjgUcYmmVC97vMiJS+vvSRsq6ksSeUzwV/BKOXDfA4U8GHbnqfIh7jLmp8iQjZnVGWFEGO/sjLjY3+PzjZCKpfzY0GshFyxT7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760337120; c=relaxed/simple; bh=h2ShKl0268FAoPcZ/un1iSkon9M56MObTMWwcYD9e/Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VnTB9qirT5RwuLO5oZXVHDSHayXM/7PGQ61FY8OadaC1A77n3bhonMfEKCdQA+nwtLuYK4brpvoehBOv6KzrvV9X2MI/nw2a5hu4zGJpSKy7JH1nEilqEzYkNZyl/5818sA3y62xz/5JdyCP5pKSwVD8h6rWd7ho51yko1UCgew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qk2sMxWz; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qk2sMxWz" X-UUID: 4e20bc32a7fe11f08d9e1119e76e3a28-20251013 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=azhD0zHbhINZX/PROKATCzykRR5K2c5OATWE6LvlLUE=; b=qk2sMxWzFOO7ZENwV2jrd5lYjr7+LrjpAfFbIYlYs4hUMwJQPQ/kn3bMVDgLqwYnw+PbOgDNwjdqdry5x7fVXBnOhUioeTHyYCtsF5nZNbw07LZgfVQnvHz4+YXrWUAXlJJqAZnqJ3b6THp+BEdAVZlWbEWqahdclm+rtLW3vAQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:29cf1d04-b0af-450a-8e2e-a93b0a246680,IP:0,UR L:25,TC:0,Content:51,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:76 X-CID-META: VersionHash:a9d874c,CLOUDID:e7a61106-56ed-4a2f-9417-82fff695211e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 3|15|50,EDM:-3,IP:nil,URL:97|99|83|106|11|1,File:130,RT:nil,Bulk:nil,QS:ni l,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC: 0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 4e20bc32a7fe11f08d9e1119e76e3a28-20251013 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 834404039; Mon, 13 Oct 2025 14:31:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 13 Oct 2025 14:31:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 13 Oct 2025 14:31:47 +0800 From: Jjian Zhou To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jjian Zhou , Chen-Yu Tsai CC: , , , , , Jjian Zhou , Krzysztof Kozlowski Subject: [PATCH v9 1/2] dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk vcp-mbox document Date: Mon, 13 Oct 2025 14:31:35 +0800 Message-ID: <20251013063146.17919-2-jjian.zhou@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251013063146.17919-1-jjian.zhou@mediatek.com> References: <20251013063146.17919-1-jjian.zhou@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The MTK VCP mailbox enables the SoC to communicate with the VCP by passing messages through 64 32-bit wide registers. It has 32 interrupt vectors in either direction for signalling purposes. This adds a binding for Mediatek VCP mailbox. Signed-off-by: Jjian Zhou Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- .../mailbox/mediatek,mt8196-vcp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt81= 96-vcp-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-= mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-m= box.yaml new file mode 100644 index 000000000000..7b1c5165e64e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.ya= ml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Video Companion Processor (VCP) mailbox + +maintainers: + - Jjian Zhou + +description: + The MTK VCP mailbox enables the SoC to communicate with the VCP by passi= ng + messages through 64 32-bit wide registers. It has 32 interrupt vectors in + either direction for signalling purposes. + +properties: + compatible: + enum: + - mediatek,mt8196-vcp-mbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + mailbox@31b80000 { + compatible =3D "mediatek,mt8196-vcp-mbox"; + reg =3D <0x31b80000 0x1000>; + interrupts =3D ; + #mbox-cells =3D <0>; + }; --=20 2.46.0 From nobody Wed Dec 17 07:40:02 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B679D2E2F1A; Mon, 13 Oct 2025 06:32:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760337123; cv=none; b=r4zaYY14hpc9/b1wKqcDRnK4dWf5JteXAqjLiWfm716b7ZA7O9fAfTtH0SHrvmktMXBfDrXKKFIbOw+kG17FD4ZZJr7xesQz97eUkuyzyQbdIPwdVt2WO672mgcml5WnXrCrdsxnlTADitV1urll9/LFc9bALuEfIqKx97QRuGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760337123; c=relaxed/simple; bh=hmte71AncTtM2fQjh+JLgM/V1JPg4L5B74jSKPxJCN8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SXWmJQVIYdQgq/Jdn/rPi0eAqCdJUuR0Yjp1NShlsbashNOPapgkImf+Sl+dwYwe0pme1IJbRcXWuBA12wKdtYGVGT0KLfwd2h4/Ekp1n/KhwzKcyMqADJvvw8eCHBUWRlz0cECBkcdKnRMjjv2BeQSfqpKPKbEvTLg+GcR04Mw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Y/OfxqOw; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Y/OfxqOw" X-UUID: 4f2b3756a7fe11f0b33aeb1e7f16c2b6-20251013 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wkb/OseJ+F5WB2VjYvd/W+5lEx/Op6IAyB60olwp448=; b=Y/OfxqOwx5wFM1GCcc55/M6Ca+HHhcXYDOrhTnw9ELUZhmk1mGtmd4IJlvspyHrzG0GxoRAU9UrTvZpX8oZGf5w45IUEXD7H5GHBQhYd1xXZa9v5F/1orxEXbT6CBg/w5gEw5FPMwSXSOP7Pf4kqhdGpdDbv3vG+B+6kG2zwY0g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:11711037-a561-4fd6-8e30-e799fe07418a,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:a9d874c,CLOUDID:cfa65102-eaf8-4c8c-94de-0bc39887e077,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 4f2b3756a7fe11f0b33aeb1e7f16c2b6-20251013 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1712147671; Mon, 13 Oct 2025 14:31:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 13 Oct 2025 14:31:50 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 13 Oct 2025 14:31:49 +0800 From: Jjian Zhou To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jjian Zhou , Chen-Yu Tsai CC: , , , , , Jjian Zhou Subject: [PATCH v9 2/2] mailbox: mediatek: Add mtk-vcp-mailbox driver Date: Mon, 13 Oct 2025 14:31:36 +0800 Message-ID: <20251013063146.17919-3-jjian.zhou@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251013063146.17919-1-jjian.zhou@mediatek.com> References: <20251013063146.17919-1-jjian.zhou@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add mtk-vcp-mailbox driver to support the communication with VCP remote microprocessor. Signed-off-by: Jjian Zhou Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/Kconfig | 9 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-vcp-mailbox.c | 170 ++++++++++++++++++++++++ include/linux/mailbox/mtk-vcp-mailbox.h | 32 +++++ 4 files changed, 213 insertions(+) create mode 100644 drivers/mailbox/mtk-vcp-mailbox.c create mode 100644 include/linux/mailbox/mtk-vcp-mailbox.h diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 29f16f220384..d7f8db25f3b3 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -304,6 +304,15 @@ config MTK_GPUEB_MBOX Say Y or m here if you want to support the MT8196 SoC in your kernel build. =20 +config MTK_VCP_MBOX + tristate "MediaTek VCP Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Say yes here to add support for the MediaTek VCP mailbox driver. + The mailbox implementation provides access from the application + processor to Video Companion Processor Unit. + If unsure say N. + config ZYNQMP_IPI_MBOX tristate "Xilinx ZynqMP IPI Mailbox" depends on ARCH_ZYNQMP && OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 81820a4f5528..944d8ea39f34 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -65,6 +65,8 @@ obj-$(CONFIG_MTK_CMDQ_MBOX) +=3D mtk-cmdq-mailbox.o =20 obj-$(CONFIG_MTK_GPUEB_MBOX) +=3D mtk-gpueb-mailbox.o =20 +obj-$(CONFIG_MTK_VCP_MBOX) +=3D mtk-vcp-mailbox.o + obj-$(CONFIG_ZYNQMP_IPI_MBOX) +=3D zynqmp-ipi-mailbox.o =20 obj-$(CONFIG_SUN6I_MSGBOX) +=3D sun6i-msgbox.o diff --git a/drivers/mailbox/mtk-vcp-mailbox.c b/drivers/mailbox/mtk-vcp-ma= ilbox.c new file mode 100644 index 000000000000..cedad575528f --- /dev/null +++ b/drivers/mailbox/mtk-vcp-mailbox.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Corporation. All rights reserved. + * Author: Jjian Zhou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_vcp_mbox { + struct mbox_controller mbox; + void __iomem *base; + struct device *dev; + const struct mtk_vcp_mbox_cfg *cfg; + struct mtk_ipi_info ipi_recv; + struct mbox_chan chans; +}; + +struct mtk_vcp_mbox_cfg { + u16 set_in; + u16 clr_out; +}; + +static irqreturn_t mtk_vcp_mbox_irq_thread(int irq, void *data) +{ + struct mtk_vcp_mbox *priv =3D data; + + /* get irq status */ + priv->ipi_recv.irq_status =3D readl(priv->base + priv->cfg->clr_out); + + __ioread32_copy(priv->ipi_recv.msg, priv->base, + MTK_VCP_MBOX_SLOT_MAX_SIZE / 4); + + mbox_chan_received_data(&priv->chans, &priv->ipi_recv); + + /* clear irq status */ + writel(priv->ipi_recv.irq_status, priv->base + priv->cfg->clr_out); + + return IRQ_HANDLED; +} + +static struct mbox_chan *mtk_vcp_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + if (sp->args_count) + return NULL; + + return &mbox->chans[0]; +} + +static int mtk_vcp_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_vcp_mbox *priv =3D chan->con_priv; + struct mtk_ipi_info *ipi_info =3D data; + u32 status; + + if (!ipi_info->msg) { + dev_err(priv->dev, "msg buffer is NULL.\n"); + return -EINVAL; + } + + status =3D readl(priv->base + priv->cfg->set_in); + if (status & BIT(ipi_info->index)) { + dev_warn(priv->dev, "mailbox IPI %d is busy.\n", ipi_info->id); + return -EBUSY; + } + + if (ipi_info->slot_ofs + ipi_info->len > MTK_VCP_MBOX_SLOT_MAX_SIZE) + return -EINVAL; + __iowrite32_copy(priv->base + ipi_info->slot_ofs, ipi_info->msg, + ipi_info->len); + + writel(BIT(ipi_info->index), priv->base + priv->cfg->set_in); + + return 0; +} + +static bool mtk_vcp_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_ipi_info *ipi_info =3D chan->active_req; + struct mtk_vcp_mbox *priv =3D chan->con_priv; + + return !(readl(priv->base + priv->cfg->set_in) & BIT(ipi_info->index)); +} + +static const struct mbox_chan_ops mtk_vcp_mbox_chan_ops =3D { + .send_data =3D mtk_vcp_mbox_send_data, + .last_tx_done =3D mtk_vcp_mbox_last_tx_done, +}; + +static int mtk_vcp_mbox_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_vcp_mbox *priv; + struct mbox_controller *mbox; + int ret, irq; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->chans.con_priv =3D priv; + mbox =3D &priv->mbox; + mbox->dev =3D dev; + mbox->ops =3D &mtk_vcp_mbox_chan_ops; + mbox->txdone_irq =3D false; + mbox->txdone_poll =3D true; + mbox->of_xlate =3D mtk_vcp_mbox_xlate; + mbox->num_chans =3D 1; + mbox->chans =3D &priv->chans; + + priv->ipi_recv.msg =3D devm_kzalloc(dev, MTK_VCP_MBOX_SLOT_MAX_SIZE, + GFP_KERNEL); + if (!priv->ipi_recv.msg) + return -ENOMEM; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->cfg =3D of_device_get_match_data(dev); + if (!priv->cfg) + return -EINVAL; + + platform_set_drvdata(pdev, priv); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_threaded_irq(dev, irq, NULL, + mtk_vcp_mbox_irq_thread, IRQF_ONESHOT, + dev_name(dev), priv); + if (ret < 0) + return ret; + + return devm_mbox_controller_register(dev, &priv->mbox); +} + +static const struct mtk_vcp_mbox_cfg mt8196_cfg =3D { + .set_in =3D 0x100, + .clr_out =3D 0x10c, +}; + +static const struct of_device_id mtk_vcp_mbox_of_match[] =3D { + { .compatible =3D "mediatek,mt8196-vcp-mbox", .data =3D &mt8196_cfg }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_vcp_mbox_of_match); + +static struct platform_driver mtk_vcp_mbox_driver =3D { + .probe =3D mtk_vcp_mbox_probe, + .driver =3D { + .name =3D "mtk_vcp_mbox", + .of_match_table =3D mtk_vcp_mbox_of_match, + }, +}; +module_platform_driver(mtk_vcp_mbox_driver); + +MODULE_AUTHOR("Jjian Zhou "); +MODULE_DESCRIPTION("MTK VCP Mailbox Controller"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/mtk-vcp-mailbox.h b/include/linux/mailbo= x/mtk-vcp-mailbox.h new file mode 100644 index 000000000000..16e59d6780a7 --- /dev/null +++ b/include/linux/mailbox/mtk-vcp-mailbox.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#ifndef __MTK_VCP_MAILBOX_H__ +#define __MTK_VCP_MAILBOX_H__ + +#define MTK_VCP_MBOX_SLOT_MAX_SIZE 0x100 /* mbox max slot size */ + +/** + * struct mtk_ipi_info - mailbox message info for mtk-vcp-mailbox + * @msg: The share buffer between IPC and mailbox driver + * @len: Message length + * @id: This is for identification purposes and not actually used + * by the mailbox hardware. + * @index: The signal number of the mailbox message. + * @slot_ofs: Data slot offset. + * @irq_status: Captures incoming signals for the RX path. + * + * It is used between IPC with mailbox driver. + */ +struct mtk_ipi_info { + void *msg; + u32 len; + u32 id; + u32 index; + u32 slot_ofs; + u32 irq_status; +}; + +#endif --=20 2.46.0