From nobody Fri Dec 19 15:19:33 2025 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010044.outbound.protection.outlook.com [40.93.198.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BD2C231832; Mon, 13 Oct 2025 06:21:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.198.44 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760336486; cv=fail; b=tWNCpgPiz1ayr+AmPXJG1QJMOcq51VRlSKrNL+tS+7hYJNHu/ID/CV1Gi83RCFdfrLgTaOWL11E5++QlwdNuQX8N3MNK11ambZN7BW6733Qpbp/mKojGplzlT5qr70VAcQc6fZSgwab4FmzCnXRLQ8LdCsRYoMC/BXrtxirwNik= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760336486; c=relaxed/simple; bh=taEfUSZ+rO4ROpLM5/fSf3Xc2EKJqtHAv1w98xSsSVo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Gpr/gISlTHTywGUmfX7bkaAaq51Rb7bWnKDpBFoR1eSy6BajREE8bKrz4VXdHQnRjxzoavn86c/4CGE5r5Mcq+J9b98kbHYe8t6htKCLp4zjK9T2NKkILpLC3opwy0RdSv38pTCSdV/fP/7QqMGwAMZR0btn50FdS9CRK2cGg2k= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=R+R2NydI; arc=fail smtp.client-ip=40.93.198.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="R+R2NydI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=i2nLC3KwIYL3dRF6beZZuvTwYx5tmmowpUwYqwk31hYotaGMBk5HPb1Z9FDRF0389xJZeB710fKKDBCoTPPXnZk2/8sPqtCjJ2DyxpHjuDqlXtRHQ9dPlDhzXl3ZQpI5Lv/93V2Oo6kg6Kl7Wve8SL0dp1HFUKskMtuJ6AFwTiZobxWqJYQdotbt4Et9+qirIC/g8ZxxOJRScuICRKlzmbT2/cREHc1GdlY7YWgPgSqkqLOs9teqc39YYjqZ/oLJlbEsdTwzzIU0AQZN7pPWTcIDHwXf1enwYHyTTS+HthTXd9t04VnipP7u6swVYw2gjufkqwt1Er9kucw6FJb8ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=j9QpMLwGnoLWw6llytpKicZ15QJlEhbetLA+I2xg2Ms=; b=aY9YQssWpHaGcSpwjFcH5ZJDLCnkFYmS4VlR9Im1ZhRM7JQaR/VH1dRtL+7idxQrfFBW+uNE5cVVGCZD75Gm7ZAsW6cQRXcz+WFSqbZLwmD4zWINZ/WbZO+lN0y01Jarbnu8gAIESzwC8owwCJQFSGt3sZ7Vq5Aroj0Q1FW2o6SCEcSsF2kEJQz7QmY7HmHAMnwyC8nkTltPlYBhUlOPtTzWk8iwmdXgXnY/YYmGv8meckTBQnDq1hFvmooGxg3+vuz/GI0RLDoPDoP2G5KkwRISoUtuCwLKJEhd0PEQ75JRYISPto5eJQOVO90/Q9hbXTAKO66Y6q62xArugfTMUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=j9QpMLwGnoLWw6llytpKicZ15QJlEhbetLA+I2xg2Ms=; b=R+R2NydIOZd3rsAeeMC+ra12CmM6z4Crnrh+FASWmksCBTSSyWObWOr5/d/ROBthSEl/pDwY6u7toimG1HmFxr2Ijx0T1DiOu84sZwZHRM9OSDMFTeYewZLjR3HICICxp8oFBturxbjTcoAp42jzeWKuY21zWJ7qooTPhxHPcAnTSp9b6oeNrscT1COVlCdkY6taALhRle+aBzEj6i9sNQ9Tb0A7m2fOvpcw1bbdIAsDhcK8XJDJULKn3QozesapQj2rgk9r89y4+eyJgYRBDYNnRQ8SBlLDgBAK04bBq1g0iI6eDNPR8UZ6PXN3OyiCG3ZrZ9y5Ls+r5K0fTxG0pg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB7726.namprd12.prod.outlook.com (2603:10b6:8:130::6) by DS0PR12MB8218.namprd12.prod.outlook.com (2603:10b6:8:f2::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9203.13; Mon, 13 Oct 2025 06:21:16 +0000 Received: from DS0PR12MB7726.namprd12.prod.outlook.com ([fe80::953f:2f80:90c5:67fe]) by DS0PR12MB7726.namprd12.prod.outlook.com ([fe80::953f:2f80:90c5:67fe%4]) with mapi id 15.20.9203.009; Mon, 13 Oct 2025 06:21:16 +0000 From: Alistair Popple To: rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, dakr@kernel.org, acourbot@nvidia.com Cc: Alistair Popple , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , John Hubbard , Joel Fernandes , Timur Tabi , linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org Subject: [PATCH v5 06/14] gpu: nova-core: Add GSP command queue bindings Date: Mon, 13 Oct 2025 17:20:32 +1100 Message-ID: <20251013062041.1639529-7-apopple@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251013062041.1639529-1-apopple@nvidia.com> References: <20251013062041.1639529-1-apopple@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SY5P282CA0194.AUSP282.PROD.OUTLOOK.COM (2603:10c6:10:249::20) To DS0PR12MB7726.namprd12.prod.outlook.com (2603:10b6:8:130::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB7726:EE_|DS0PR12MB8218:EE_ X-MS-Office365-Filtering-Correlation-Id: e5242b13-dfcb-4eed-3274-08de0a20b701 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MfrjgmhK0DauR4zhX0cxuCI/CFCUyb0agqoj2TJc9k+F4leSCYOSBmOcx25T?= =?us-ascii?Q?2eG7Qq6cu2z9jv3I9C94FwCWPFV36B/JcG3cYlXX5MJp0lgtoX9msXcaB/Ug?= =?us-ascii?Q?GuWOnbhBrTqmpf8aD6a5kZljndxT343QGJ1t5U8769zUo5+LIIcNXRJPnmiz?= =?us-ascii?Q?6FOGcB9dQnW5tmULtK3RNn+d4stWX1GjLxTwrwOr1x5uEtSr6zTQ0a3ESKpH?= =?us-ascii?Q?sUz1KrFdwWvm0EuobbVdNbBVrYcC2ZOhNAidRreF51JuP0yTOVXgRfygEvAv?= =?us-ascii?Q?1ui8ERi4VG7d7D1k4TZ1r6IlhWJfj2Ba2rXoBCKhegjVHuoHCMuWZv4sS0M5?= =?us-ascii?Q?JURc9Ow0VF1ZWzptnDr3qM7QCyAXH0FKAWaKa3kB+xBHu/TdSdTPJScqRla8?= =?us-ascii?Q?oDteMX1DOT6Z4r2AVxHkQ6tT+TO+2Do9jZD0uGTlbAMSzrcqZW1Crnt2FCW1?= =?us-ascii?Q?RL330kG004EYTWpO3JjR1pZSL0+e5ahMXjp+u7NjV6LK7zs9oxt5G9n5iyGU?= =?us-ascii?Q?7XcR6u3W8G/lLh2dBLbHHdYI/Kj4DBtrJ3XHEC+KYqV43suhMxi0OrMbPpUN?= =?us-ascii?Q?xrmlg8P3ctK/dkag18+XW7aJjIb3Dg13jSeRyzMY7xrqU/aW0TMhr5Qxei1O?= =?us-ascii?Q?pYewfNWBchdVRqUvkdwloJb5vXOUVBla0SAS7UqAoe/wUorroX3d7ZKfKOaY?= =?us-ascii?Q?RhRwWd5O3wVElMtLMCkNv3nX07P4JkfrtR+sV/WTbM8UZxnqXn6c/1I8p/MN?= =?us-ascii?Q?vjnVtBO4hHBpgieM7xsSTfq5eRZlMpyxbAyIu8kvCtwigUco8+Lch1xsseEr?= =?us-ascii?Q?Sqr5gmEVt1F4h+OmGGUOyqKK/wXoO2JhXuEt1alYsYNL635fQ1kKjsu0i7Ar?= =?us-ascii?Q?GYp83kB5HHZAgi60W7HchlmS+MzaPI+Nrl8i5NtjpvjfKYGn5p4pBk2PkAJp?= =?us-ascii?Q?tUdRf2oTM9qRAhRfxdayftl0gxTR2WP89mbBgaDSuEQ+frk/myqmfpUjzBiS?= =?us-ascii?Q?/8n8DU18yB895uBOlPZGD/AmthIWEvH2h+v0J/LlqNnOG9PYnb6ftKbpXd7C?= =?us-ascii?Q?lmT2wbZelg63eBEsC1Od1MyPNpmO8dWMqgDX7vRF5Ce5MErQ2WZsFRsj07O1?= =?us-ascii?Q?1Oo10PgBjkyaP5i28rW1swkqk4bKPa5yI0rKbVBE9JbbZQM/j68BlWBCqnTB?= =?us-ascii?Q?ptevuAu1eoXQFTj+Lt7xEcehTqrSBdM7Z0OoYu7KLV6OIEDKiBEl2HN8nLYd?= =?us-ascii?Q?eifcwg3wXDA3HMt32vSN4RVl/PWG686bVvPLNZycAnyNY94lBboBGCd1b+Kw?= =?us-ascii?Q?dUfkEFN3t1Y6KRTOr/kblsN7H9Xfn0xE48jhNYrmvfWvdWtn8Ehbil+3yb4B?= =?us-ascii?Q?tWRmBzsmc3tR2JNpTC9RJUiIZjcxaYYbwWcLtatRGa8JN1mdAZsJ0uh8s1MJ?= =?us-ascii?Q?/JtJj1fDXLbOdX5A69s1OmHSq1qO7lJt?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB7726.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014)(7416014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?zYOvnTJu8w0nUS69YGdwRxFpfD535KOXhJF5h5WnYNQTvLEZkYMCdeiOfFGH?= =?us-ascii?Q?f96oSt4Z7NLWCHRYWrp7EDIqn5W2eim0X5O/9k1OudXDra0eQ3WNWZ8uzjR3?= =?us-ascii?Q?L4GwRiq4dPl7R93829fEeQOBDi+JtV53rKCeBk+BVqSMT55q6HEbcn4eIrkv?= =?us-ascii?Q?sfPkEfzQEfTYCNjQrxSdczcSDkJnoZnqXQE6ACbzDkcF59Fc0yjABKE9Ih0T?= =?us-ascii?Q?1V4qj8U/VwjQEvSvXQxr7DB4wovheh6GrqVRHaKQBBHNgfYejeCdYUI7COrG?= =?us-ascii?Q?AtLMfDlSxIMgBPV+En+S/9g7RruDbIIAyVqkYB3uWp2YDgfLfwDFFjcVfKjp?= =?us-ascii?Q?3q9EmRfybMg5lmBQkob1rta6Dj04CHpC8IxfDBXteKbETbendUKZYcaLbWCM?= =?us-ascii?Q?pxPPjNMbZAKkHDnRCWoEnspRzk3HBaISLyzyNmkaHUxKrArPfF+KM/6NYlWa?= =?us-ascii?Q?YheYEmaLgGlO3CnBtaTNo7kS+6IEdjVi343/ukLYs9GT8imRe00fQ3yKB7SC?= =?us-ascii?Q?zRou7NgvLEOc9ANuSe9O0Ncq/EJacbSjPRUla2f/3KXrPRHXLFn101PxSHNw?= =?us-ascii?Q?CFqQwE1lM6RgxgKHs7xs8UYQTNQb/56F37D1042J/GJBzvcLksdvAc5CHzan?= =?us-ascii?Q?1MmOkWmB908tWu0y9ij6Bt8cM9ykQWaWiZtHWoj5qovnuPFBFdpETPghdCkY?= =?us-ascii?Q?hpm6tTHIwrZPit7t4/c6cx22YSuMKOytxwv4/kRi3E3+YW0hGI+5c23VEnzH?= =?us-ascii?Q?W81XE4CP+hZdRNGjBoPBRzyN2xfcPkbNI2X4fLXzxG/7oLwTA4ojJeUKIeRn?= =?us-ascii?Q?cYTLM3UOcPz6A9LQrDKWkTrmy44mx29wwsuBkA9ZcSWfzc50WInAM2TUoDI/?= =?us-ascii?Q?9GpKQEg6BKBWzet296UeTzvJ4cQ3xKtiwNNShabQEuNXdWXzo5EmDjSnsAEq?= =?us-ascii?Q?4dXhrDYBc+OIK0J5KAGT0qShy6VlXxveV/U2ibGGU6A8EXqA7QmlpB0zPGCm?= =?us-ascii?Q?3WJLBa8Jp/E1u8ID6EPsFKiFm/Erul7Oajp7qlXOLdX5v175RBLrXk7PKToM?= =?us-ascii?Q?Dcr4F+HipOQQ6eWNhwA1geTLjeYn6L/FVn0KbQPQZpreNfDR261xEMeUJaer?= =?us-ascii?Q?tmF9TV6whvAhA0P8uolvLPWHOgB3tR5d5ET8/QzL4P7lmjXBQrXUpEBEVwnZ?= =?us-ascii?Q?Yc+T6F5MOjaXYCwt1P0w8rqYChV+5SM02EBfTsgNorM7B62p+ma2ZLL1ip/c?= =?us-ascii?Q?4Xv5rEUgUjMa8Fme3U4kfUA5L1Z69NcnHbVARjNhYRyddT5yk2Qg2YFsF5P/?= =?us-ascii?Q?AcCId0Mn232r4z9mlWyHw0UcskKrwu8SzzB0p4ZqjN1XIF9Yel/k7hDphSt5?= =?us-ascii?Q?fBgJNEXIX+4ppPMh3rJWNRL5BLXCVYt22GqvUDAuXzftSWlODOLqGPWuA/3z?= =?us-ascii?Q?w+HM3AY9y4t5sOPwluxV+pgR0jX+P33+y8x5KWsR7Rq05EL9s9ooMYLsSyUq?= =?us-ascii?Q?P57AsemLhVJr8D9PZgxDov1DYFs6qUA2TUQPYo5xH9OXQUg+48cmDkwvalww?= =?us-ascii?Q?/OCRJEZHMJzdb5jIrO/qNBvbBiBPrvfqmxvIQVSQ?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e5242b13-dfcb-4eed-3274-08de0a20b701 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB7726.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 06:21:16.2463 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CRfuc/uqpTZnYYb+o1ovdLrHN+UyEDh8E0tym11pj4wX9zxhsTkGfVFbTPgpzQoNebpMIXgGk+ZTOG1aAJv5Sg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8218 Content-Type: text/plain; charset="utf-8" Add bindings and accessors used for the GSP command queue. Signed-off-by: Alistair Popple --- Changes for v5: - Derive the Zeroable trait for structs and enums Changes for v4: - Don't panic the kernel if trying to initialise a large (> 4GB) message header. - Use `init!` to provide safe and complete initialisers. - Take an enum type instead of a u32 for the function. Changes for v3: - New for v3 --- drivers/gpu/nova-core/gsp/fw.rs | 275 +++++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 541 ++++++++++++++++++ 2 files changed, 816 insertions(+) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 1cc992ca492c..a2ce570ddfaf 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -5,6 +5,7 @@ // Alias to avoid repeating the version number with every use. use r570_144 as bindings; =20 +use core::fmt; use core::ops::Range; =20 use kernel::dma::CoherentAllocation; @@ -16,6 +17,7 @@ use crate::firmware::gsp::GspFirmware; use crate::gpu::Chipset; use crate::gsp::FbLayout; +use crate::gsp::GSP_PAGE_SIZE; =20 /// Dummy type to group methods related to heap parameters for running the= GSP firmware. pub(crate) struct GspFwHeapParams(()); @@ -158,6 +160,120 @@ pub(crate) fn new(gsp_firmware: &GspFirmware, fb_layo= ut: &FbLayout) -> Self { } } =20 +#[derive(PartialEq)] +pub(crate) enum MsgFunction { + // Common function codes + Nop =3D bindings::NV_VGPU_MSG_FUNCTION_NOP as isize, + SetGuestSystemInfo =3D bindings::NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM= _INFO as isize, + AllocRoot =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_ROOT as isize, + AllocDevice =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE as isize, + AllocMemory =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY as isize, + AllocCtxDma =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA as isize, + AllocChannelDma =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA a= s isize, + MapMemory =3D bindings::NV_VGPU_MSG_FUNCTION_MAP_MEMORY as isize, + BindCtxDma =3D bindings::NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA as isize, + AllocObject =3D bindings::NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT as isize, + Free =3D bindings::NV_VGPU_MSG_FUNCTION_FREE as isize, + Log =3D bindings::NV_VGPU_MSG_FUNCTION_LOG as isize, + GetGspStaticInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INF= O as isize, + SetRegistry =3D bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY as isize, + GspSetSystemInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INF= O as isize, + GspInitPostObjGpu =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJ= GPU as isize, + GspRmControl =3D bindings::NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL as isiz= e, + GetStaticInfo =3D bindings::NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO as is= ize, + + // Event codes + GspInitDone =3D bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE as isize, + GspRunCpuSequencer =3D bindings::NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENC= ER as isize, + PostEvent =3D bindings::NV_VGPU_MSG_EVENT_POST_EVENT as isize, + RcTriggered =3D bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED as isize, + MmuFaultQueued =3D bindings::NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED as isi= ze, + OsErrorLog =3D bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG as isize, + GspPostNoCat =3D bindings::NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD as = isize, + GspLockdownNotice =3D bindings::NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE = as isize, + UcodeLibOsPrint =3D bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT as i= size, +} + +impl fmt::Display for MsgFunction { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + // Common function codes + MsgFunction::Nop =3D> write!(f, "NOP"), + MsgFunction::SetGuestSystemInfo =3D> write!(f, "SET_GUEST_SYST= EM_INFO"), + MsgFunction::AllocRoot =3D> write!(f, "ALLOC_ROOT"), + MsgFunction::AllocDevice =3D> write!(f, "ALLOC_DEVICE"), + MsgFunction::AllocMemory =3D> write!(f, "ALLOC_MEMORY"), + MsgFunction::AllocCtxDma =3D> write!(f, "ALLOC_CTX_DMA"), + MsgFunction::AllocChannelDma =3D> write!(f, "ALLOC_CHANNEL_DMA= "), + MsgFunction::MapMemory =3D> write!(f, "MAP_MEMORY"), + MsgFunction::BindCtxDma =3D> write!(f, "BIND_CTX_DMA"), + MsgFunction::AllocObject =3D> write!(f, "ALLOC_OBJECT"), + MsgFunction::Free =3D> write!(f, "FREE"), + MsgFunction::Log =3D> write!(f, "LOG"), + MsgFunction::GetGspStaticInfo =3D> write!(f, "GET_GSP_STATIC_I= NFO"), + MsgFunction::SetRegistry =3D> write!(f, "SET_REGISTRY"), + MsgFunction::GspSetSystemInfo =3D> write!(f, "GSP_SET_SYSTEM_I= NFO"), + MsgFunction::GspInitPostObjGpu =3D> write!(f, "GSP_INIT_POST_O= BJGPU"), + MsgFunction::GspRmControl =3D> write!(f, "GSP_RM_CONTROL"), + MsgFunction::GetStaticInfo =3D> write!(f, "GET_STATIC_INFO"), + + // Event codes + MsgFunction::GspInitDone =3D> write!(f, "INIT_DONE"), + MsgFunction::GspRunCpuSequencer =3D> write!(f, "RUN_CPU_SEQUEN= CER"), + MsgFunction::PostEvent =3D> write!(f, "POST_EVENT"), + MsgFunction::RcTriggered =3D> write!(f, "RC_TRIGGERED"), + MsgFunction::MmuFaultQueued =3D> write!(f, "MMU_FAULT_QUEUED"), + MsgFunction::OsErrorLog =3D> write!(f, "OS_ERROR_LOG"), + MsgFunction::GspPostNoCat =3D> write!(f, "NOCAT"), + MsgFunction::GspLockdownNotice =3D> write!(f, "LOCKDOWN_NOTICE= "), + MsgFunction::UcodeLibOsPrint =3D> write!(f, "LIBOS_PRINT"), + } + } +} + +impl TryFrom for MsgFunction { + type Error =3D kernel::error::Error; + + fn try_from(value: u32) -> Result { + match value { + bindings::NV_VGPU_MSG_FUNCTION_NOP =3D> Ok(MsgFunction::Nop), + bindings::NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO =3D> { + Ok(MsgFunction::SetGuestSystemInfo) + } + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_ROOT =3D> Ok(MsgFunction:= :AllocRoot), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE =3D> Ok(MsgFunctio= n::AllocDevice), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY =3D> Ok(MsgFunctio= n::AllocMemory), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA =3D> Ok(MsgFuncti= on::AllocCtxDma), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA =3D> Ok(MsgFu= nction::AllocChannelDma), + bindings::NV_VGPU_MSG_FUNCTION_MAP_MEMORY =3D> Ok(MsgFunction:= :MapMemory), + bindings::NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA =3D> Ok(MsgFunctio= n::BindCtxDma), + bindings::NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT =3D> Ok(MsgFunctio= n::AllocObject), + bindings::NV_VGPU_MSG_FUNCTION_FREE =3D> Ok(MsgFunction::Free), + bindings::NV_VGPU_MSG_FUNCTION_LOG =3D> Ok(MsgFunction::Log), + bindings::NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO =3D> Ok(Msg= Function::GetGspStaticInfo), + bindings::NV_VGPU_MSG_FUNCTION_SET_REGISTRY =3D> Ok(MsgFunctio= n::SetRegistry), + bindings::NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO =3D> Ok(Msg= Function::GspSetSystemInfo), + bindings::NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU =3D> { + Ok(MsgFunction::GspInitPostObjGpu) + } + bindings::NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL =3D> Ok(MsgFunct= ion::GspRmControl), + bindings::NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO =3D> Ok(MsgFunc= tion::GetStaticInfo), + bindings::NV_VGPU_MSG_EVENT_GSP_INIT_DONE =3D> Ok(MsgFunction:= :GspInitDone), + bindings::NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER =3D> { + Ok(MsgFunction::GspRunCpuSequencer) + } + bindings::NV_VGPU_MSG_EVENT_POST_EVENT =3D> Ok(MsgFunction::Po= stEvent), + bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED =3D> Ok(MsgFunction::= RcTriggered), + bindings::NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED =3D> Ok(MsgFuncti= on::MmuFaultQueued), + bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG =3D> Ok(MsgFunction::= OsErrorLog), + bindings::NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD =3D> Ok(MsgF= unction::GspPostNoCat), + bindings::NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE =3D> Ok(MsgFun= ction::GspLockdownNotice), + bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT =3D> Ok(MsgFunct= ion::UcodeLibOsPrint), + _ =3D> Err(EINVAL), + } + } +} + /// Struct containing the arguments required to pass a memory buffer to th= e GSP /// for use during initialisation. /// @@ -208,3 +324,162 @@ fn id8(name: &str) -> u64 { })) } } + +#[repr(transparent)] +pub(crate) struct MsgqTxHeader(bindings::msgqTxHeader); + +impl MsgqTxHeader { + pub(crate) fn new(msgq_size: u32, rx_hdr_offset: u32, msg_count: u32) = -> Self { + Self(bindings::msgqTxHeader { + version: 0, + size: msgq_size, + msgSize: GSP_PAGE_SIZE as u32, + msgCount: msg_count, + writePtr: 0, + flags: 1, + rxHdrOff: rx_hdr_offset, + entryOff: GSP_PAGE_SIZE as u32, + }) + } + + pub(crate) fn write_ptr(&self) -> u32 { + let ptr =3D (&self.0.writePtr) as *const u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_read! macro would and is therefore s= afe + // for the same reasons. + unsafe { ptr.read_volatile() } + } + + pub(crate) fn set_write_ptr(&mut self, val: u32) { + let ptr =3D (&mut self.0.writePtr) as *mut u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_write! macro would and is therefore = safe + // for the same reasons. + unsafe { ptr.write_volatile(val) } + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for MsgqTxHeader {} + +/// RX header for setting up a message queue with the GSP. +#[repr(transparent)] +pub(crate) struct MsgqRxHeader(bindings::msgqRxHeader); + +impl MsgqRxHeader { + pub(crate) fn new() -> Self { + Self(Default::default()) + } + + pub(crate) fn read_ptr(&self) -> u32 { + let ptr =3D (&self.0.readPtr) as *const u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_read! macro would and is therefore s= afe + // for the same reasons. + unsafe { ptr.read_volatile() } + } + + pub(crate) fn set_read_ptr(&mut self, val: u32) { + let ptr =3D (&mut self.0.readPtr) as *mut u32; + + // SAFETY: This is part of a CoherentAllocation and implements the + // equivalent as what the dma_write! macro would and is therefore = safe + // for the same reasons. + unsafe { ptr.write_volatile(val) } + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for MsgqRxHeader {} + +impl bindings::rpc_message_header_v { + pub(crate) fn init(cmd_size: u32, function: MsgFunction) -> impl Init<= Self, Error> { + type RpcMessageHeader =3D bindings::rpc_message_header_v; + try_init!(RpcMessageHeader { + // TODO: magic number + header_version: 0x03000000, + signature: bindings::NV_VGPU_MSG_SIGNATURE_VALID, + function: function as u32, + length: (size_of::() as u32) + .checked_add(cmd_size) + .ok_or(EOVERFLOW)?, + rpc_result: 0xffffffff, + rpc_result_private: 0xffffffff, + ..Zeroable::init_zeroed() + }) + } +} + +// SAFETY: We can't derive the Zeroable trait for this binding because the +// procedural macro doesn't support the syntax used by bindgen to create t= he +// __IncompleteArrayField types. So instead we implement it here, which is= safe +// because these are explicitly padded structures only containing types for +// which any bit pattern, including all zeros, is valid. +unsafe impl Zeroable for bindings::rpc_message_header_v {} + +#[repr(transparent)] +pub(crate) struct GspMsgElement { + inner: bindings::GSP_MSG_QUEUE_ELEMENT, +} + +impl GspMsgElement { + #[allow(non_snake_case)] + pub(crate) fn init( + sequence: u32, + cmd_size: usize, + function: MsgFunction, + ) -> impl Init { + type RpcMessageHeader =3D bindings::rpc_message_header_v; + type InnerGspMsgElement =3D bindings::GSP_MSG_QUEUE_ELEMENT; + let init_inner =3D try_init!(InnerGspMsgElement { + seqNum: sequence, + elemCount: size_of::() + .checked_add(cmd_size) + .ok_or(EOVERFLOW)? + .div_ceil(GSP_PAGE_SIZE) as u32, + rpc <- RpcMessageHeader::init(cmd_size as u32, function), + ..Zeroable::init_zeroed() + }); + + try_init!(GspMsgElement { + inner <- init_inner, + }) + } + + pub(crate) fn set_checksum(&mut self, checksum: u32) { + self.inner.checkSum =3D checksum; + } + + // Return the total length of the message, noting that rpc.length incl= udes + // the length of the GspRpcHeader but not the message header. + pub(crate) fn length(&self) -> u32 { + size_of::() as u32 - size_of::() as u32 + + self.inner.rpc.length + } + + pub(crate) fn sequence(&self) -> u32 { + self.inner.rpc.sequence + } + + pub(crate) fn function_number(&self) -> u32 { + self.inner.rpc.function + } + + pub(crate) fn function(&self) -> Result { + self.inner.rpc.function.try_into() + } + + pub(crate) fn element_count(&self) -> u32 { + self.inner.elemCount + } +} + +// SAFETY: Padding is explicit and will not contain uninitialized data. +unsafe impl AsBytes for GspMsgElement {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns +// are valid. +unsafe impl FromBytes for GspMsgElement {} diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index f7b38978c5f8..1251b0c313ce 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -1,5 +1,36 @@ // SPDX-License-Identifier: GPL-2.0 =20 +#[repr(C)] +#[derive(Default)] +pub struct __IncompleteArrayField(::core::marker::PhantomData, [T; 0= ]); +impl __IncompleteArrayField { + #[inline] + pub const fn new() -> Self { + __IncompleteArrayField(::core::marker::PhantomData, []) + } + #[inline] + pub fn as_ptr(&self) -> *const T { + self as *const _ as *const T + } + #[inline] + pub fn as_mut_ptr(&mut self) -> *mut T { + self as *mut _ as *mut T + } + #[inline] + pub unsafe fn as_slice(&self, len: usize) -> &[T] { + ::core::slice::from_raw_parts(self.as_ptr(), len) + } + #[inline] + pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] { + ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len) + } +} +impl ::core::fmt::Debug for __IncompleteArrayField { + fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Re= sult { + fmt.write_str("__IncompleteArrayField") + } +} +pub const NV_VGPU_MSG_SIGNATURE_VALID: u32 =3D 1129337430; pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 =3D 0; pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 =3D 23068672; pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 =3D 8388608; @@ -11,6 +42,7 @@ pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 =3D 280; pub const GSP_FW_WPR_META_REVISION: u32 =3D 1; pub const GSP_FW_WPR_META_MAGIC: i64 =3D -2577556379034558285; +pub const REGISTRY_TABLE_ENTRY_TYPE_DWORD: u32 =3D 1; pub type __u8 =3D ffi::c_uchar; pub type __u16 =3D ffi::c_ushort; pub type __u32 =3D ffi::c_uint; @@ -19,6 +51,477 @@ pub type u16_ =3D __u16; pub type u32_ =3D __u32; pub type u64_ =3D __u64; +pub const NV_VGPU_MSG_FUNCTION_NOP: _bindgen_ty_2 =3D 0; +pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO: _bindgen_ty_2 =3D 1; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_ROOT: _bindgen_ty_2 =3D 2; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE: _bindgen_ty_2 =3D 3; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY: _bindgen_ty_2 =3D 4; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA: _bindgen_ty_2 =3D 5; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA: _bindgen_ty_2 =3D 6; +pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY: _bindgen_ty_2 =3D 7; +pub const NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA: _bindgen_ty_2 =3D 8; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT: _bindgen_ty_2 =3D 9; +pub const NV_VGPU_MSG_FUNCTION_FREE: _bindgen_ty_2 =3D 10; +pub const NV_VGPU_MSG_FUNCTION_LOG: _bindgen_ty_2 =3D 11; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM: _bindgen_ty_2 =3D 12; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY: _bindgen_ty_2 =3D 13; +pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA: _bindgen_ty_2 =3D 14; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA: _bindgen_ty_2 =3D 15; +pub const NV_VGPU_MSG_FUNCTION_GET_EDID: _bindgen_ty_2 =3D 16; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL: _bindgen_ty_2 =3D 17; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT: _bindgen_ty_2 =3D 18; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE: _bindgen_ty_2 =3D 19; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY: _bindgen_ty_2 =3D 20; +pub const NV_VGPU_MSG_FUNCTION_DUP_OBJECT: _bindgen_ty_2 =3D 21; +pub const NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS: _bindgen_ty_2 =3D 22; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_EVENT: _bindgen_ty_2 =3D 23; +pub const NV_VGPU_MSG_FUNCTION_SEND_EVENT: _bindgen_ty_2 =3D 24; +pub const NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL: _bindgen_ty_2 =3D 25; +pub const NV_VGPU_MSG_FUNCTION_DMA_CONTROL: _bindgen_ty_2 =3D 26; +pub const NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM: _bindgen_ty_2 =3D 27; +pub const NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE: _bindgen_ty_2 =3D 28; +pub const NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA: _bindgen_ty_2 =3D 2= 9; +pub const NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT: _bindgen_ty_2 =3D 30; +pub const NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT: _bindgen_ty_2 =3D 31; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE: _bindgen_ty_2 =3D 32; +pub const NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL: _bindgen_ty_2 =3D 33; +pub const NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API: _bindgen_ty_2 =3D 34; +pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ: _bindgen_ty_2 =3D 35; +pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE: _bindgen_ty_2 =3D 36; +pub const NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA: _bindgen_ty= _2 =3D 37; +pub const NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT: _bindgen_ty_2 =3D 38; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO: _bindgen_ty_2 =3D 39; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE: _bindgen_ty_2 =3D = 40; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO: _bindgen_ty_2= =3D 41; +pub const NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO: _bindgen_ty_2 =3D 42; +pub const NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY: _bindgen_ty_2 =3D 43; +pub const NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY: _bindgen_ty_2 =3D 44; +pub const NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES: _bindgen_ty_2 =3D 4= 5; +pub const NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE: _bindgen_ty_2 =3D 46; +pub const NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER: _bindgen_ty_2 =3D 4= 7; +pub const NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE: _bindgen_ty_2 =3D 48; +pub const NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA: _bindgen_ty_2 =3D 49; +pub const NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS: _bindgen_ty_2 =3D 50; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO: _bindgen_ty_2 =3D 51; +pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM: _bindgen_ty_2 =3D 52; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2: _bindgen_ty_2 =3D 53; +pub const NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY: _bindgen_ty_2 =3D 54; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO: _bindgen_ty_2 =3D 5= 5; +pub const NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES: _bindgen_ty_2 =3D= 56; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_57: _bindgen_ty_2 =3D 57; +pub const NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT: _bindgen_ty_2 =3D= 58; +pub const NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE: _bindgen_ty_= 2 =3D 59; +pub const NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION: _bindgen_ty_2 =3D 6= 0; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES: _bindgen_ty_2 =3D 61; +pub const NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY: _bindgen_ty_2 =3D 62; +pub const NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32: _bindgen_ty_2 =3D 63; +pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT: _bindgen_ty_2 = =3D 64; +pub const NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO: _bindgen_ty_2 =3D 65; +pub const NV_VGPU_MSG_FUNCTION_RMFS_INIT: _bindgen_ty_2 =3D 66; +pub const NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE: _bindgen_ty_2 =3D 67; +pub const NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP: _bindgen_ty_2 =3D 68; +pub const NV_VGPU_MSG_FUNCTION_RMFS_TEST: _bindgen_ty_2 =3D 69; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE: _bindgen_ty_2 =3D 70; +pub const NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD: _bindgen_ty_2 =3D 71; +pub const NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO: _bindgen_ty_2 =3D 72; +pub const NV_VGPU_MSG_FUNCTION_SET_REGISTRY: _bindgen_ty_2 =3D 73; +pub const NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU: _bindgen_ty_2 =3D 74; +pub const NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION: _bindgen_ty_= 2 =3D 75; +pub const NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: _bindgen_ty_2 =3D 76; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2: _bindgen_ty_2 =3D 77; +pub const NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT: _bindgen_ty_2 =3D = 78; +pub const NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY: _bindgen_ty_2 =3D 79; +pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO: _bindgen_ty_2= =3D 80; +pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER: _bindgen_ty_2 = =3D 81; +pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER: _bindgen_ty_2= =3D 82; +pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER: _= bindgen_ty_2 =3D 83; +pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER:= _bindgen_ty_2 =3D 84; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE: _bindgen_ty_2 =3D 8= 5; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO: _bindgen= _ty_2 =3D 86; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO: _bindgen= _ty_2 =3D 87; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL: _bindgen_ty_2 =3D 88; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL: _bindgen_ty_2 = =3D 89; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT: _bindgen_ty_2= =3D 90; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO: _bindgen_ty_2 = =3D 91; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST: _bindgen_ty_2 =3D 92; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL: _bindgen_ty= _2 =3D 93; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE: _bindgen_ty_2 =3D= 94; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR: _bindgen_ty_2 =3D= 95; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR: _bindgen_ty_2 =3D= 96; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE: _bindgen_ty_2 =3D 97; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE: _bindgen_ty_2 =3D 98; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT: _bindgen_ty_2 =3D 99; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS: _bindgen_ty_2 = =3D 100; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL: _bindgen_ty_= 2 =3D 101; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL: _bindgen= _ty_2 =3D 102; +pub const NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: _bindgen_ty_2 =3D 103; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2: _bindgen_ty_2 =3D 104; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT: _bindgen_ty_2 =3D = 105; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY: _bindgen_ty_2 =3D = 106; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS: _bindgen_ty= _2 =3D 107; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES: _bindge= n_ty_2 =3D 108; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES: _bindgen= _ty_2 =3D 109; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK: _bindgen_ty_2 = =3D 110; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX: _bindgen_ty_2 =3D 111; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND: _bindgen_ty_= 2 =3D 112; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE: _bindgen= _ty_2 =3D 113; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND: _bindgen_ty_2 =3D= 114; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX: _bindgen_ty_2 =3D = 115; +pub const NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES: _bi= ndgen_ty_2 =3D 116; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT: _bindgen_ty_2 = =3D 117; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES: _bindgen_ty_= 2 =3D 118; +pub const NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS: _bindgen_ty_2 = =3D 119; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE: _bindgen_ty_2= =3D 120; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK: _bindgen_ty_2 =3D 121; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY: _bindgen_ty= _2 =3D 122; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK: _bindgen_ty_2= =3D 123; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS: _bindgen_ty_2 =3D 1= 24; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS: _bindgen_ty_2 =3D 125; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX: _bindgen_ty_2 =3D= 126; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_0: _bindgen_ty_2 =3D 127; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC: _bindgen_ty_2 = =3D 128; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY: _bindgen_ty_2 =3D= 129; +pub const NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS: _bindgen_ty_2 =3D 1= 30; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES: _bindgen_ty_2 =3D 1= 31; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT: _bindgen_ty_2 =3D= 132; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT: _bindgen_ty_2 =3D = 133; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS: _bindgen_ty_2 =3D 13= 4; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG: _bindgen_ty_2 = =3D 135; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE: _bindg= en_ty_2 =3D 136; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE: _bind= gen_ty_2 =3D 137; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG: _bindgen_ty= _2 =3D 138; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE: _bindg= en_ty_2 =3D 139; +pub const NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM: _bindgen_ty_2 =3D 14= 0; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT: _bindgen_ty= _2 =3D 141; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2: _bindgen_ty_2 =3D 142; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES: _bindgen_= ty_2 =3D 143; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = =3D 144; +pub const NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES: _bindgen_ty_2= =3D 145; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX: _bindgen_ty_2 =3D 146; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO: _bindgen_ty_2 =3D 147; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO: _bindgen_ty_2 = =3D 148; +pub const NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL: _bindgen_ty_2 =3D 149; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE: _bindgen_ty_2 =3D= 150; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS: _bindgen_ty= _2 =3D 151; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL: _bindgen_t= y_2 =3D 152; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM: _bindgen_ty_2 =3D 153; +pub const NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ: _bindgen_ty_2 = =3D 154; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB: _bind= gen_ty_2 =3D 155; +pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO: _bindgen_t= y_2 =3D 156; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP: _bindge= n_ty_2 =3D 157; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE: _bindgen_ty= _2 =3D 158; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE: _bindgen_ty= _2 =3D 159; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE: _bindgen_ty_2 = =3D 160; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY: _bindgen_ty_2 = =3D 161; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP: _bindgen_ty_2 =3D 1= 62; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP: _bindgen_ty_2 =3D= 163; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM: _bindgen_ty= _2 =3D 164; +pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES: _bindgen_ty= _2 =3D 165; +pub const NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION: _b= indgen_ty_2 =3D 166; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL: _bindgen= _ty_2 =3D 167; +pub const NV_VGPU_MSG_FUNCTION_DCE_RM_INIT: _bindgen_ty_2 =3D 168; +pub const NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER: _bindgen_ty_= 2 =3D 169; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET: _bindgen_ty_2= =3D 170; +pub const NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND: _bindgen_ty_2 =3D= 171; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2: _bindgen_ty= _2 =3D 172; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM: _bi= ndgen_ty_2 =3D 173; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE: _bindgen_ty_2 =3D = 174; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS:= _bindgen_ty_2 =3D 175; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE: _bindgen_ty_= 2 =3D 176; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO: _bindgen_ty_= 2 =3D 177; +pub const NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS: _bindgen_ty_2 =3D 178; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE: _bindgen_ty_2 = =3D 179; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS: _bindgen_ty_2 =3D 18= 0; +pub const NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA: _bindgen_ty_2 =3D 18= 1; +pub const NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA: _bindgen_ty_2 =3D= 182; +pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED: _b= indgen_ty_2 =3D 183; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE: _bindgen_ty_2 = =3D 184; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE: _bindgen_ty_2 = =3D 185; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN: _bindgen= _ty_2 =3D 186; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_IND= EX: _bindgen_ty_2 =3D 187; +pub const NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPER= ATION: _bindgen_ty_2 =3D + 188; +pub const NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT= _INTR_MASK: + _bindgen_ty_2 =3D 189; +pub const NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER: _bin= dgen_ty_2 =3D 190; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS: _bindgen_ty_2 = =3D 191; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING: _bindgen_ty_2 =3D= 192; +pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING: _bindgen_ty_2 = =3D 193; +pub const NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK: _bindgen= _ty_2 =3D 194; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS: _bindgen_ty_2 =3D = 195; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS: _bindgen_ty_2 = =3D 196; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS: _bindgen_ty_2 =3D 197; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS: _bindgen_ty_2 =3D 198; +pub const NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER: _bindgen_ty_2 =3D = 199; +pub const NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB: _bindgen_ty_2 =3D 200; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS: _bindgen_ty_2 = =3D 201; +pub const NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK: _bindgen_ty_2 =3D 2= 02; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG: _bindgen_ty_2 = =3D 203; +pub const NV_VGPU_MSG_FUNCTION_RM_API_CONTROL: _bindgen_ty_2 =3D 204; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE: _= bindgen_ty_2 =3D 205; +pub const NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA: _bind= gen_ty_2 =3D 206; +pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA: _bindgen_ty_2 =3D 207; +pub const NV_VGPU_MSG_FUNCTION_RESERVED_208: _bindgen_ty_2 =3D 208; +pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2: _bindgen_ty_2 =3D 209; +pub const NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS: _bindgen_ty_2 =3D 210; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA: _bindgen_= ty_2 =3D 211; +pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO: _bindgen_ty_2= =3D 212; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE: _bindg= en_ty_2 =3D 213; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR: _bindgen_ty_2 = =3D 214; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS: _bindge= n_ty_2 =3D 215; +pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS: _bindg= en_ty_2 =3D 216; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG: _bindgen_t= y_2 =3D 217; +pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG: _bindgen_t= y_2 =3D 218; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES: _bindgen_ty_2 =3D 219; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES: _bindgen_ty_2 =3D 220; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF: _bindgen_ty_2 =3D 22= 1; +pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF: _bindgen_ty_2 =3D 22= 2; +pub const NV_VGPU_MSG_FUNCTION_RESERVED: _bindgen_ty_2 =3D 223; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL: _bindg= en_ty_2 =3D 224; +pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_HS_CREDITS_MAPPING: _bindgen_t= y_2 =3D 225; +pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_EXPORT: _bindgen_ty_2 = =3D 226; +pub const NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS: _bindgen_ty_2 =3D 227; +pub type _bindgen_ty_2 =3D ffi::c_uint; +pub const NV_VGPU_MSG_EVENT_FIRST_EVENT: _bindgen_ty_3 =3D 4096; +pub const NV_VGPU_MSG_EVENT_GSP_INIT_DONE: _bindgen_ty_3 =3D 4097; +pub const NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: _bindgen_ty_3 =3D 4098; +pub const NV_VGPU_MSG_EVENT_POST_EVENT: _bindgen_ty_3 =3D 4099; +pub const NV_VGPU_MSG_EVENT_RC_TRIGGERED: _bindgen_ty_3 =3D 4100; +pub const NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED: _bindgen_ty_3 =3D 4101; +pub const NV_VGPU_MSG_EVENT_OS_ERROR_LOG: _bindgen_ty_3 =3D 4102; +pub const NV_VGPU_MSG_EVENT_RG_LINE_INTR: _bindgen_ty_3 =3D 4103; +pub const NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES: _bindgen_ty_3 = =3D 4104; +pub const NV_VGPU_MSG_EVENT_SIM_READ: _bindgen_ty_3 =3D 4105; +pub const NV_VGPU_MSG_EVENT_SIM_WRITE: _bindgen_ty_3 =3D 4106; +pub const NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK: _bindgen_ty_3 =3D= 4107; +pub const NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT: _bindgen_ty_3 =3D 4108; +pub const NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: _bindgen_ty_3 =3D 4= 109; +pub const NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK: _bindgen_= ty_3 =3D 4110; +pub const NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE: _bindgen_ty_3 =3D= 4111; +pub const NV_VGPU_MSG_EVENT_VGPU_CONFIG: _bindgen_ty_3 =3D 4112; +pub const NV_VGPU_MSG_EVENT_DISPLAY_MODESET: _bindgen_ty_3 =3D 4113; +pub const NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE: _bindgen_ty_3 =3D 4114; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _bindgen_ty_3= =3D 4115; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512: _bindgen_ty_3= =3D 4116; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024: _bindgen_ty_= 3 =3D 4117; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048: _bindgen_ty_= 3 =3D 4118; +pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096: _bindgen_ty_= 3 =3D 4119; +pub const NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE: _bindgen_ty_3 =3D 412= 0; +pub const NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED: _bindgen_ty_3 =3D 4121; +pub const NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK: _bindgen_ty= _3 =3D 4122; +pub const NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: _bindgen_ty_3 =3D 4123; +pub const NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _bindgen_ty_3 =3D 4124; +pub const NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: _bindgen_ty_3 =3D 4125; +pub const NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE: _bindgen_ty_3 =3D 4126; +pub const NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY: _bindgen_ty_3 =3D= 4127; +pub const NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: _bindgen_ty_3 =3D 4128; +pub const NV_VGPU_MSG_EVENT_FECS_ERROR: _bindgen_ty_3 =3D 4129; +pub const NV_VGPU_MSG_EVENT_RECOVERY_ACTION: _bindgen_ty_3 =3D 4130; +pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 =3D 4131; +pub type _bindgen_ty_3 =3D ffi::c_uint; +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct DOD_METHOD_DATA { + pub status: u32_, + pub acpiIdListLen: u32_, + pub acpiIdList: [u32_; 16usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct JT_METHOD_DATA { + pub status: u32_, + pub jtCaps: u32_, + pub jtRevId: u16_, + pub bSBIOSCaps: u8_, + pub __bindgen_padding_0: u8, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct MUX_METHOD_DATA_ELEMENT { + pub acpiId: u32_, + pub mode: u32_, + pub status: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct MUX_METHOD_DATA { + pub tableLen: u32_, + pub acpiIdMuxModeTable: [MUX_METHOD_DATA_ELEMENT; 16usize], + pub acpiIdMuxPartTable: [MUX_METHOD_DATA_ELEMENT; 16usize], + pub acpiIdMuxStateTable: [MUX_METHOD_DATA_ELEMENT; 16usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct CAPS_METHOD_DATA { + pub status: u32_, + pub optimusCaps: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct ACPI_METHOD_DATA { + pub bValid: u8_, + pub __bindgen_padding_0: [u8; 3usize], + pub dodMethodData: DOD_METHOD_DATA, + pub jtMethodData: JT_METHOD_DATA, + pub muxMethodData: MUX_METHOD_DATA, + pub capsMethodData: CAPS_METHOD_DATA, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct BUSINFO { + pub deviceID: u16_, + pub vendorID: u16_, + pub subdeviceID: u16_, + pub subvendorID: u16_, + pub revisionID: u8_, + pub __bindgen_padding_0: u8, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GSP_VF_INFO { + pub totalVFs: u32_, + pub firstVFOffset: u32_, + pub FirstVFBar0Address: u64_, + pub FirstVFBar1Address: u64_, + pub FirstVFBar2Address: u64_, + pub b64bitBar0: u8_, + pub b64bitBar1: u8_, + pub b64bitBar2: u8_, + pub __bindgen_padding_0: [u8; 5usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GSP_PCIE_CONFIG_REG { + pub linkCap: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GspSystemInfo { + pub gpuPhysAddr: u64_, + pub gpuPhysFbAddr: u64_, + pub gpuPhysInstAddr: u64_, + pub gpuPhysIoAddr: u64_, + pub nvDomainBusDeviceFunc: u64_, + pub simAccessBufPhysAddr: u64_, + pub notifyOpSharedSurfacePhysAddr: u64_, + pub pcieAtomicsOpMask: u64_, + pub consoleMemSize: u64_, + pub maxUserVa: u64_, + pub pciConfigMirrorBase: u32_, + pub pciConfigMirrorSize: u32_, + pub PCIDeviceID: u32_, + pub PCISubDeviceID: u32_, + pub PCIRevisionID: u32_, + pub pcieAtomicsCplDeviceCapMask: u32_, + pub oorArch: u8_, + pub __bindgen_padding_0: [u8; 7usize], + pub clPdbProperties: u64_, + pub Chipset: u32_, + pub bGpuBehindBridge: u8_, + pub bFlrSupported: u8_, + pub b64bBar0Supported: u8_, + pub bMnocAvailable: u8_, + pub chipsetL1ssEnable: u32_, + pub bUpstreamL0sUnsupported: u8_, + pub bUpstreamL1Unsupported: u8_, + pub bUpstreamL1PorSupported: u8_, + pub bUpstreamL1PorMobileOnly: u8_, + pub bSystemHasMux: u8_, + pub upstreamAddressValid: u8_, + pub FHBBusInfo: BUSINFO, + pub chipsetIDInfo: BUSINFO, + pub __bindgen_padding_1: [u8; 2usize], + pub acpiMethodData: ACPI_METHOD_DATA, + pub hypervisorType: u32_, + pub bIsPassthru: u8_, + pub __bindgen_padding_2: [u8; 7usize], + pub sysTimerOffsetNs: u64_, + pub gspVFInfo: GSP_VF_INFO, + pub bIsPrimary: u8_, + pub isGridBuild: u8_, + pub __bindgen_padding_3: [u8; 2usize], + pub pcieConfigReg: GSP_PCIE_CONFIG_REG, + pub gridBuildCsp: u32_, + pub bPreserveVideoMemoryAllocations: u8_, + pub bTdrEventSupported: u8_, + pub bFeatureStretchVblankCapable: u8_, + pub bEnableDynamicGranularityPageArrays: u8_, + pub bClockBoostSupported: u8_, + pub bRouteDispIntrsToCPU: u8_, + pub __bindgen_padding_4: [u8; 6usize], + pub hostPageSize: u64_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct MESSAGE_QUEUE_INIT_ARGUMENTS { + pub sharedMemPhysAddr: u64_, + pub pageTableEntryCount: u32_, + pub __bindgen_padding_0: [u8; 4usize], + pub cmdQueueOffset: u64_, + pub statQueueOffset: u64_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GSP_SR_INIT_ARGUMENTS { + pub oldLevel: u32_, + pub flags: u32_, + pub bInPMTransition: u8_, + pub __bindgen_padding_0: [u8; 3usize], +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GSP_ARGUMENTS_CACHED { + pub messageQueueInitArguments: MESSAGE_QUEUE_INIT_ARGUMENTS, + pub srInitArguments: GSP_SR_INIT_ARGUMENTS, + pub gpuInstance: u32_, + pub bDmemStack: u8_, + pub __bindgen_padding_0: [u8; 7usize], + pub profilerArgs: GSP_ARGUMENTS_CACHED__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct GSP_ARGUMENTS_CACHED__bindgen_ty_1 { + pub pa: u64_, + pub size: u64_, +} +#[repr(C)] +#[derive(Copy, Clone, Zeroable)] +pub union rpc_message_rpc_union_field_v03_00 { + pub spare: u32_, + pub cpuRmGfid: u32_, +} +impl Default for rpc_message_rpc_union_field_v03_00 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +pub type rpc_message_rpc_union_field_v =3D rpc_message_rpc_union_field_v03= _00; +#[repr(C)] +pub struct rpc_message_header_v03_00 { + pub header_version: u32_, + pub signature: u32_, + pub length: u32_, + pub function: u32_, + pub rpc_result: u32_, + pub rpc_result_private: u32_, + pub sequence: u32_, + pub u: rpc_message_rpc_union_field_v, + pub rpc_message_data: __IncompleteArrayField, +} +impl Default for rpc_message_header_v03_00 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +pub type rpc_message_header_v =3D rpc_message_header_v03_00; #[repr(C)] #[derive(Copy, Clone, Zeroable)] pub struct GspFwWprMeta { @@ -145,3 +648,41 @@ pub struct LibosMemoryRegionInitArgument { pub loc: u8_, pub __bindgen_padding_0: [u8; 6usize], } +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct msgqTxHeader { + pub version: u32_, + pub size: u32_, + pub msgSize: u32_, + pub msgCount: u32_, + pub writePtr: u32_, + pub flags: u32_, + pub rxHdrOff: u32_, + pub entryOff: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone, Zeroable)] +pub struct msgqRxHeader { + pub readPtr: u32_, +} +#[repr(C)] +#[repr(align(8))] +#[derive(Zeroable)] +pub struct GSP_MSG_QUEUE_ELEMENT { + pub authTagBuffer: [u8_; 16usize], + pub aadBuffer: [u8_; 16usize], + pub checkSum: u32_, + pub seqNum: u32_, + pub elemCount: u32_, + pub __bindgen_padding_0: [u8; 4usize], + pub rpc: rpc_message_header_v, +} +impl Default for GSP_MSG_QUEUE_ELEMENT { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} --=20 2.50.1