From nobody Thu Dec 18 00:07:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59F1230AD0A; Tue, 14 Oct 2025 03:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760411545; cv=none; b=HDMbO/fkaBThE404HFVvfoR0Jx3Jq19pJPXSPmyqRw4zXOBmuW0f7zGnGet93w8bELDGlwoQLwI+rjn4lExZu8y7+oiKLsdFlNw6YuWpKlPceuhwiBBm/KZjWEIdfA03rpzjXgwMgd0maNj1kpehfAwNbqMcx2LUeel+Y21F7CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760411545; c=relaxed/simple; bh=v2BADzYfnq+K1fzHmT4PyhtQoFp+N4lgGjYFoXj/QVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WMQJQMLV0QXT47zq9NRolgePaf+KvBRUT3GHikVwNynV/o6n5s5u7LSshpJkeWMJs/XgHUVVwH2+EIUYI/3KLJnKGiGYAJICm72EHPjnE0oa7z9lg1MxgVXRXJpR3DvgiH84dUy2nmcovNKPwRzJN6ZJdQx5A0chK8xRajdJHGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E50wZMvz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E50wZMvz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F01B5C19421; Tue, 14 Oct 2025 03:12:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760411544; bh=v2BADzYfnq+K1fzHmT4PyhtQoFp+N4lgGjYFoXj/QVg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=E50wZMvzN6UGn8W9qOicIH0YvZaqDqUdd4BX4DHzU97/21FlZJ1kyq1xyRTudcUSX gPooprxqPRwcl0PNSnm2SLCP4KmqxKe0lU1rwNFPtE1LGGPSkmA/XfgSIIiEs5V9TC 3hMErI01ION6gD9oEBJny35BII8ATn6uVSv2g0yjn+aZuZIchmCZCmSZ3V2ZyRYTKO hMX/wrdgymKSF4T1UBzT8q1iJlugNMOOhqr2wVRitzwECLlbF1yEUVU+Y/X169jHDN k/3pYBdFx/F6mA/QkSXfChqYwJw9V3Q5zZ6AfHAqVxKSA6WBzF8Ndw37Hhzbtzmq1c dGRNcUyYGD6/g== From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:58 -0700 Subject: [PATCH v3 6/8] riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-tt-bh-dts-v3-6-9f058d4bbbda@oss.tenstorrent.com> References: <20251013-tt-bh-dts-v3-0-9f058d4bbbda@oss.tenstorrent.com> In-Reply-To: <20251013-tt-bh-dts-v3-0-9f058d4bbbda@oss.tenstorrent.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Daniel Lezcano , Thomas Gleixner , Anup Patel , Arnd Bergmann , Joel Stanley , Joel Stanley , Nicholas Piggin , Michael Neuling , Michael Ellerman , Andy Gross , Anirudh Srinivasan , Drew Fustini , Paul Walmsley , Albert Ou Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley X-Mailer: b4 0.14.2 From: Drew Fustini Add device tree source describing the Tenstorrent Blackhole SoC and the Blackhole P100 and P150 PCIe cards. There are no differences between the P100 and P150 cards from the perspective of an OS kernel like Linux running on the X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. CONFIG_HVC_RISCV_SBI needs to be enabled. The boot script on the host adds 'console=3Dhvc0' so that the full boot output appears in the console program on the host. Link: https://github.com/tenstorrent/opensbi/ Link: https://github.com/tenstorrent/tt-bh-linux Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/tenstorrent/Makefile | 2 + arch/riscv/boot/dts/tenstorrent/blackhole-card.dts | 14 +++ arch/riscv/boot/dts/tenstorrent/blackhole.dtsi | 108 +++++++++++++++++= ++++ 5 files changed, 126 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5a29636b2df010296cabead26a6f9e557747928a..b49471cc31397cd0f21ea363ea0= af50baf5b9eaf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22165,6 +22165,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/tenstorrent/linux.git F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml +F: arch/riscv/boot/dts/tenstorrent/ =20 RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70ac659d00948241f4263dec62c548c..cf179c6253ce223b5e909691b42= fdbd16f846d57 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -9,4 +9,5 @@ subdir-y +=3D sifive subdir-y +=3D sophgo subdir-y +=3D spacemit subdir-y +=3D starfive +subdir-y +=3D tenstorrent subdir-y +=3D thead diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts= /tenstorrent/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2c81faaba46235821470b077392= ebfebd37ef55a --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TENSTORRENT) +=3D blackhole-card.dtb diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts b/arch/risc= v/boot/dts/tenstorrent/blackhole-card.dts new file mode 100644 index 0000000000000000000000000000000000000000..f53667ce73a947051816ed35ce3= b78189b8aacb7 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "blackhole.dtsi" + +/ { + model =3D "Tenstorrent Blackhole"; + compatible =3D "tenstorrent,blackhole-card", "tenstorrent,blackhole"; + + memory@400030000000 { + device_type =3D "memory"; + reg =3D <0x4000 0x30000000 0x1 0x00000000>; + }; +}; diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/bo= ot/dts/tenstorrent/blackhole.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6408810d8d80d230e7cbaf2744b= bfce1788499ee --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright 2025 Tenstorrent AI ULC +/dts-v1/; + +/ { + compatible =3D "tenstorrent,blackhole"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <50000000>; + + cpu@0 { + compatible =3D "sifive,x280", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + mmu-type =3D "riscv,sv57"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu@1 { + compatible =3D "sifive,x280", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + mmu-type =3D "riscv,sv57"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu@2 { + compatible =3D "sifive,x280", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + mmu-type =3D "riscv,sv57"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu@3 { + compatible =3D "sifive,x280", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + mmu-type =3D "riscv,sv57"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + clint0: timer@2000000 { + compatible =3D "tenstorrent,blackhole-clint", "sifive,clint0"; + reg =3D <0x0 0x2000000 0x0 0x10000>; + interrupts-extended =3D <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, + <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, + <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, + <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; + }; + + plic0: interrupt-controller@c000000 { + compatible =3D "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x0c000000 0x0 0x04000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + riscv,ndev =3D <128>; + }; + }; +}; --=20 2.34.1