From nobody Thu Dec 18 00:07:20 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30D1D3081B1; Tue, 14 Oct 2025 03:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760411542; cv=none; b=HE37SKxWydtWLmYl6elM4CpLPyqu0UdwZmIlB9Gmdkf8TrhWYU/by3FFXszIU0M1uX9QgIoAhcMRNZre1AU6UoHRomUaV0LciVKfhCEVvv6cEpzimd0ncI7ARVL3C3hgydRKIzhc8oVQCbt29I5o8Cj2UCVEY8GZrMej/mabOGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760411542; c=relaxed/simple; bh=Wl8ZTHg5stOwe+WQ7WFdplzC0h58N4FuSj3zEehF9Xg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AyQ0uu/4LfCvg2HpS4ivAIVfeOaYGkxdX79wJ0OKTCq7YW+YdnzW7sesuTS1B04kzYYYkAFBeHsQeY97wx0dNemCwEQ0P0MgYDtp6g5wZtS7parA2MDx2Um58CnzqX9Vp0pZr9woeaJwXJQjwe44CZU4lcLLx8WMo7pxqPI/SFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qkbHR7kT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qkbHR7kT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9398C19422; Tue, 14 Oct 2025 03:12:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760411541; bh=Wl8ZTHg5stOwe+WQ7WFdplzC0h58N4FuSj3zEehF9Xg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qkbHR7kTwiXYWvQ/fqj9y5/T2xFH11ApqwV3le2acP+rBlVlsz6yhj3XtmZ2BqTVY inL5VcNcNrveffFMR0sYm32gZgr+MW9TtSilPvPoS++y5WlRM0caIxQD0y0ndeAVtL muBruj/y6CEVxVgAXwu4ZHGommIVioG0YkJTmlKjO+C9gV910eoZ4vv8tY2FGSD+KA L2Pe/RtUuJOURIWlaE5vXfPDIlU4pcelXSprDdhNvd+7CyZyQJw/er8QRzTd7NvjMQ PPHO5dp1f5HJHbtQawmcz7CpNAirurNb5hspUPmYXkEzHMmiiG2e2s/IAG5g5NnJEh zD0skIu+s1RIQ== From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:55 -0700 Subject: [PATCH v3 3/8] dt-bindings: riscv: cpus: Add SiFive X280 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-tt-bh-dts-v3-3-9f058d4bbbda@oss.tenstorrent.com> References: <20251013-tt-bh-dts-v3-0-9f058d4bbbda@oss.tenstorrent.com> In-Reply-To: <20251013-tt-bh-dts-v3-0-9f058d4bbbda@oss.tenstorrent.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , Daniel Lezcano , Thomas Gleixner , Anup Patel , Arnd Bergmann , Joel Stanley , Joel Stanley , Nicholas Piggin , Michael Neuling , Michael Ellerman , Andy Gross , Anirudh Srinivasan , Drew Fustini , Paul Walmsley , Albert Ou Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley X-Mailer: b4 0.14.2 From: Drew Fustini Document compatible for the SiFive X280 RISC-V core. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb39d39219e138792f4cb831cb88dc..afb8533f6a081bd9b91e13e3018= 5f99ec2d5dc3b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -70,6 +70,7 @@ properties: - enum: - sifive,e51 - sifive,u54-mc + - sifive,x280 - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only --=20 2.34.1