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[35.204.138.224]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63b7334cb4bsm5392310a12.44.2025.10.12.22.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Oct 2025 22:27:17 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 13 Oct 2025 06:27:16 +0100 Subject: [PATCH v2] clk: samsung: clk-pll: simplify samsung_pll_lock_wait() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-samsung-clk-pll-simplification-v2-1-b9aab610878c@linaro.org> X-B4-Tracking: v=1; b=H4sIALON7GgC/42NQQ6CMBBFr0K6dkxn1CiuvIdhUWEKE0tLWmw0h LtbOYHL95P/3qISR+GkrtWiImdJEnwB2lWqHYzvGaQrrEjTCbVGSGZML99D654wOQdJxsmJldb M5QoH1mQvNRISqSKZIlt5b4F7U3iQNIf42XoZf+vf6oyA0CF1bGs+Hx90c+JNDPsQe9Ws6/oFz htrRc0AAAA= X-Change-ID: 20251001-samsung-clk-pll-simplification-3e02f8912122 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: Peter Griffin , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Protsenko , =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 readl_relaxed_poll_timeout_atomic() has been updated in 2023 in commit 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_atomic()") to avoid usage of timekeeping APIs. It also never used udelay() when no delay was given. With the implementation avoiding timekeeping APIs, and with a caller not passing a delay, the timeout argument simply becomes a loop counter. Therefore the code here can be simplified to unconditionally use readl_relaxed_poll_timeout_atomic(). The difference being the last argument, the timeout (loop counter). Simply adjust it to pass the more generous counter in all cases. This change also allows us to drop all code around the pll_early_timeout variable as it is unused now. Reviewed-by: Sam Protsenko Signed-off-by: Andr=C3=A9 Draszik --- Changes in v2: - drop pll_early_timeout (Krzysztof) - drop timekeeping.h - collect tags - Link to v1: https://lore.kernel.org/r/20251001-samsung-clk-pll-simplifica= tion-v1-1-d12def9e74b2@linaro.org --- drivers/clk/samsung/clk-pll.c | 41 ++++++++++-----------------------------= -- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d..0a8fc9649ae2975b1b19669fd51= 92bae984aa57b 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -11,14 +11,12 @@ #include #include #include -#include #include #include #include "clk.h" #include "clk-pll.h" =20 -#define PLL_TIMEOUT_US 20000U -#define PLL_TIMEOUT_LOOPS 1000000U +#define PLL_TIMEOUT_LOOPS 20000U =20 struct samsung_clk_pll { struct clk_hw hw; @@ -71,20 +69,11 @@ static int samsung_pll_determine_rate(struct clk_hw *hw, return 0; } =20 -static bool pll_early_timeout =3D true; - -static int __init samsung_pll_disable_early_timeout(void) -{ - pll_early_timeout =3D false; - return 0; -} -arch_initcall(samsung_pll_disable_early_timeout); - /* Wait until the PLL is locked */ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, unsigned int reg_mask) { - int i, ret; + int ret; u32 val; =20 /* @@ -93,25 +82,15 @@ static int samsung_pll_lock_wait(struct samsung_clk_pll= *pll, * initialized, another when the timekeeping is suspended. udelay() also * cannot be used when the clocksource is not running on arm64, since * the current timer is used as cycle counter. So a simple busy loop - * is used here in that special cases. The limit of iterations has been - * derived from experimental measurements of various PLLs on multiple - * Exynos SoC variants. Single register read time was usually in range - * 0.4...1.5 us, never less than 0.4 us. + * is used here. + * The limit of iterations has been derived from experimental + * measurements of various PLLs on multiple Exynos SoC variants. Single + * register read time was usually in range 0.4...1.5 us, never less than + * 0.4 us. */ - if (pll_early_timeout || timekeeping_suspended) { - i =3D PLL_TIMEOUT_LOOPS; - while (i-- > 0) { - if (readl_relaxed(pll->con_reg) & reg_mask) - return 0; - - cpu_relax(); - } - ret =3D -ETIMEDOUT; - } else { - ret =3D readl_relaxed_poll_timeout_atomic(pll->con_reg, val, - val & reg_mask, 0, PLL_TIMEOUT_US); - } - + ret =3D readl_relaxed_poll_timeout_atomic(pll->con_reg, val, + val & reg_mask, 0, + PLL_TIMEOUT_LOOPS); if (ret < 0) pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); =20 --- base-commit: 2b763d4652393c90eaa771a5164502ec9dd965ae change-id: 20251001-samsung-clk-pll-simplification-3e02f8912122 Best regards, --=20 Andr=C3=A9 Draszik