From nobody Fri Dec 19 17:18:22 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5362A29AB1A; Mon, 13 Oct 2025 17:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377668; cv=none; b=iA71DIVMYDN5N0MGjh07+qEAfNKcqx1+I1gw8wUZ+nXthtIGSzYpUBtOVkJH1R4J41y9gulgHcGVEe6R3CDu9b8CzYcJQSDVeJtRRp/n5fvs8R5+6lgrkOyO8yi0zxWtn1oBveL6WCHS7kZRNxymbKollJ9XKi48idCNDIv/Gyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377668; c=relaxed/simple; bh=LlxOX0XdXGOPt3oDaTbfcdhtJfrWKo6DQBQFWyQqX78=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aPEzwTV4myWknh/M+jZ5BDLMTvUL9TQUd+4H2qwsGeeyDgQUJWUlca1Np6G5iKD5yN1usJTZlM3q89u6p1+c77Es4S50D61pn2L3Vld5GZmgapbUhgddkL5I7ArnYxDpHLbiuX9NOVFKywpF+1/8jFTUkNO3h5sliJ02+z5jZ5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s5G6GReD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s5G6GReD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5C78C116B1; Mon, 13 Oct 2025 17:47:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377667; bh=LlxOX0XdXGOPt3oDaTbfcdhtJfrWKo6DQBQFWyQqX78=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s5G6GReDfu7EobXs19mLrzGPdFL55sM1gsACHZxoUUTdSZTbp7IhPh9idUciZ7Wf+ hbb4KrgLBny0irXbzF3sbFDUWcGAEaP+NXMeni0ky4HAkCjJWK3vlXKuEoiJtH5/TX jOLGVS7R1ActZlJ6xVyLbRCd5Ys/5Z+UZqWc7bvYOq1zHubd92XXGA5zJfXV1Kvj3H N8EcwGKsTtpInSM2RF0BNrCjILCVOI7O2ZVZdaziFL8VGaMq7dkoTfPz0j1JMigQbw eip5P4w9bTYX5LBRFwuWYjVJ/jRejhw6DZcyFWRLjOEFoQoaaV8pKDnVgRPFnIxjSG i5W5+cIUbtGxA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Date: Mon, 13 Oct 2025 18:45:33 +0100 Message-ID: <20251013-posting-alright-8f945a4bebfd@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2941; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=W/92o0rvdQPG7KvXPwubOldJUAMEfyDDSsE844RVnYI=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrfbr6kyrsTRy3z7FrEv6xe399bPylN4G3Vl9LeDJK Zn1MaaaHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIlzcjw2wOw/ZlG19HOXIb ZZ+IvPE5V/LeBo68+vybpz9ydITWVjEyvHonNFNGKuzWdWeD94uCVjs85Dv10f1g3ULhxfU/Oj3 9eAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley "mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a= 4fefe@wendy/ [1] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- v3: - drop simple-mfd at Krzysztof's request since the child nodes do not yet exist. v2: - clean up various minor comments from Rob on mpfs-mss-top-sysreg - remove mpfs-control-scb from this patch --- .../microchip,mpfs-mss-top-sysreg.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 000000000000..1ab691db8795 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + reg =3D <0x20002000 0x1000>; + #reset-cells =3D <1>; + }; + --=20 2.51.0