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[83.21.75.22]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63a5c32249esm8729019a12.41.2025.10.13.06.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 06:42:06 -0700 (PDT) From: Artur Weber Date: Mon, 13 Oct 2025 15:41:54 +0200 Subject: [PATCH v7 7/7] clk: bcm281xx: Add corresponding bus clocks for peripheral clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-kona-bus-clock-v7-7-8f473d99ae19@gmail.com> References: <20251013-kona-bus-clock-v7-0-8f473d99ae19@gmail.com> In-Reply-To: <20251013-kona-bus-clock-v7-0-8f473d99ae19@gmail.com> To: Michael Turquette , Stephen Boyd , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alex Elder , Stanislav Jakubek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, phone-devel@vger.kernel.org, Artur Weber X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6005; i=aweber.kernel@gmail.com; h=from:subject:message-id; bh=BKr8nVscrBQotunl8u3eUCru7U4bR7e46blB/UH7zYk=; b=owEBbQKS/ZANAwAKAbO7+KEToFFoAcsmYgBo7QGg6q+Yc21Ig+afa32iNWFNzvHv7ZkWVlH2N 0Em92Ym7byJAjMEAAEKAB0WIQTmYwAOrB3szWrSiQ2zu/ihE6BRaAUCaO0BoAAKCRCzu/ihE6BR aMTLEACdZNtR5aTmug+rai2D1xBgUuBhee96uc7gCs6JjvgMPMffeAChVUIytsllR71lj74m9mf g5X6AS9hbUWdkzNGZl8jslulemey9NH8A9W19Ld9XejQDTWGQtv9RTZ4mAHagi0m/pCoBf8b9H4 vfM+34HRFfV05296MrCfT1kFibzDvgCKHZzEgvvM/B0J+X6hDtwezVfRi9tlarMvORZEUhaY9xu dM+WKd1ZUpvyc+oaFMSpxtEfkmhCR3fk8P7EANYZ/D/HOf17SiSA3Cw386UdyFoiESu43w35qlo zGFooOq+OowrQDWkutSUHsQrMGes5RP5twZL+9EpOIBcsesKO7mtOMxwAcbE9f35Ey91Q/kwL2R WzwoecopMZZB2Hcim6Qw6zZNFUyB1Z+5likC1QeAON1Gd2uGbKo+n31B9sXk0Af3vuYErD6ZqZj fxUBic+06J2pgC4tWVDQ+hp9H/dOeGxAUnD/G6DlFiYHJjrCIKbynMWNsecBhKPg0oA5+XUh+aZ yY66HmUc7Tcma0giwX2YK6SpQ/sDjOaAZWjkTiVJqr2nChHDthpLFt9/b1FvoDVgCJ6LWOCzlCp pFrMW7Q6KqHQUq4M/QLCWwICtIy+qvpOE2q7WDv4NRyMsdQtt6ClLslQy7E1MLymsEztaHR3oNH Ks8sp5Chwqk+k3Q== X-Developer-Key: i=aweber.kernel@gmail.com; a=openpgp; fpr=E663000EAC1DECCD6AD2890DB3BBF8A113A05168 Add bus clocks corresponding to peripheral clocks currently supported by the BCM281xx clock driver. Reviewed-by: Florian Fainelli Signed-off-by: Artur Weber --- Changes in v4: - Adapt to CLOCK_COUNT -> CLK_COUNT rename Changes in v3: - Adapt to CLOCK_COUNT defines being moved Changes in v2: - Add this patch (BCM281xx bus clocks) --- drivers/clk/bcm/clk-bcm281xx.c | 127 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 124 insertions(+), 3 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm281xx.c b/drivers/clk/bcm/clk-bcm281xx.c index 62c3bf465625..13fd8a5ea8fa 100644 --- a/drivers/clk/bcm/clk-bcm281xx.c +++ b/drivers/clk/bcm/clk-bcm281xx.c @@ -59,7 +59,17 @@ static struct peri_clk_data pmu_bsc_var_data =3D { .trig =3D TRIGGER(0x0a40, 2), }; =20 -#define BCM281XX_AON_CCU_CLK_COUNT (BCM281XX_AON_CCU_PMU_BSC_VAR + 1) +static struct bus_clk_data hub_timer_apb_data =3D { + .gate =3D HW_SW_GATE(0x0414, 18, 3, 2), + .hyst =3D HYST(0x0414, 10, 11), +}; + +static struct bus_clk_data pmu_bsc_apb_data =3D { + .gate =3D HW_SW_GATE(0x0418, 18, 3, 2), + .hyst =3D HYST(0x0418, 10, 11), +}; + +#define BCM281XX_AON_CCU_CLK_COUNT (BCM281XX_AON_CCU_PMU_BSC_APB + 1) =20 static struct ccu_data aon_ccu_data =3D { BCM281XX_CCU_COMMON(aon, AON), @@ -70,6 +80,10 @@ static struct ccu_data aon_ccu_data =3D { KONA_CLK(aon, pmu_bsc, peri), [BCM281XX_AON_CCU_PMU_BSC_VAR] =3D KONA_CLK(aon, pmu_bsc_var, peri), + [BCM281XX_AON_CCU_HUB_TIMER_APB] =3D + KONA_CLK(aon, hub_timer_apb, bus), + [BCM281XX_AON_CCU_PMU_BSC_APB] =3D + KONA_CLK(aon, pmu_bsc_apb, bus), [BCM281XX_AON_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; @@ -178,7 +192,36 @@ static struct peri_clk_data hsic2_12m_data =3D { .trig =3D TRIGGER(0x0afc, 5), }; =20 -#define BCM281XX_MASTER_CCU_CLK_COUNT (BCM281XX_MASTER_CCU_HSIC2_12M + 1) +static struct bus_clk_data sdio1_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0358, 16, 1, 0), +}; + +static struct bus_clk_data sdio2_ahb_data =3D { + .gate =3D HW_SW_GATE(0x035c, 16, 1, 0), +}; + +static struct bus_clk_data sdio3_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0364, 16, 1, 0), +}; + +static struct bus_clk_data sdio4_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0360, 16, 1, 0), +}; + +static struct bus_clk_data usb_ic_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0354, 16, 1, 0), +}; + +/* also called usbh_ahb */ +static struct bus_clk_data hsic2_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0370, 16, 1, 0), +}; + +static struct bus_clk_data usb_otg_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0348, 16, 1, 0), +}; + +#define BCM281XX_MASTER_CCU_CLK_COUNT (BCM281XX_MASTER_CCU_USB_OTG_AHB + 1) =20 static struct ccu_data master_ccu_data =3D { BCM281XX_CCU_COMMON(master, MASTER), @@ -197,6 +240,20 @@ static struct ccu_data master_ccu_data =3D { KONA_CLK(master, hsic2_48m, peri), [BCM281XX_MASTER_CCU_HSIC2_12M] =3D KONA_CLK(master, hsic2_12m, peri), + [BCM281XX_MASTER_CCU_SDIO1_AHB] =3D + KONA_CLK(master, sdio1_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO2_AHB] =3D + KONA_CLK(master, sdio2_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO3_AHB] =3D + KONA_CLK(master, sdio3_ahb, bus), + [BCM281XX_MASTER_CCU_SDIO4_AHB] =3D + KONA_CLK(master, sdio4_ahb, bus), + [BCM281XX_MASTER_CCU_USB_IC_AHB] =3D + KONA_CLK(master, usb_ic_ahb, bus), + [BCM281XX_MASTER_CCU_HSIC2_AHB] =3D + KONA_CLK(master, hsic2_ahb, bus), + [BCM281XX_MASTER_CCU_USB_OTG_AHB] =3D + KONA_CLK(master, usb_otg_ahb, bus), [BCM281XX_MASTER_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; @@ -309,7 +366,51 @@ static struct peri_clk_data pwm_data =3D { .trig =3D TRIGGER(0x0afc, 15), }; =20 -#define BCM281XX_SLAVE_CCU_CLK_COUNT (BCM281XX_SLAVE_CCU_PWM + 1) +static struct bus_clk_data uartb_apb_data =3D { + .gate =3D HW_SW_GATE(0x0400, 16, 1, 0), +}; + +static struct bus_clk_data uartb2_apb_data =3D { + .gate =3D HW_SW_GATE(0x0404, 16, 1, 0), +}; + +static struct bus_clk_data uartb3_apb_data =3D { + .gate =3D HW_SW_GATE(0x0408, 16, 1, 0), +}; + +static struct bus_clk_data uartb4_apb_data =3D { + .gate =3D HW_SW_GATE(0x040c, 16, 1, 0), +}; + +static struct bus_clk_data ssp0_apb_data =3D { + .gate =3D HW_SW_GATE(0x0410, 16, 1, 0), +}; + +static struct bus_clk_data ssp2_apb_data =3D { + .gate =3D HW_SW_GATE(0x0418, 16, 1, 0), +}; + +static struct bus_clk_data bsc1_apb_data =3D { + .gate =3D HW_SW_GATE(0x0458, 16, 1, 0), + .hyst =3D HYST(0x0458, 8, 9), +}; + +static struct bus_clk_data bsc2_apb_data =3D { + .gate =3D HW_SW_GATE(0x045c, 16, 1, 0), + .hyst =3D HYST(0x045c, 8, 9), +}; + +static struct bus_clk_data bsc3_apb_data =3D { + .gate =3D HW_SW_GATE(0x0484, 16, 1, 0), + .hyst =3D HYST(0x0484, 8, 9), +}; + +static struct bus_clk_data pwm_apb_data =3D { + .gate =3D HW_SW_GATE(0x0468, 16, 1, 0), + .hyst =3D HYST(0x0468, 8, 9), +}; + +#define BCM281XX_SLAVE_CCU_CLK_COUNT (BCM281XX_SLAVE_CCU_PWM_APB + 1) =20 static struct ccu_data slave_ccu_data =3D { BCM281XX_CCU_COMMON(slave, SLAVE), @@ -334,6 +435,26 @@ static struct ccu_data slave_ccu_data =3D { KONA_CLK(slave, bsc3, peri), [BCM281XX_SLAVE_CCU_PWM] =3D KONA_CLK(slave, pwm, peri), + [BCM281XX_SLAVE_CCU_UARTB_APB] =3D + KONA_CLK(slave, uartb_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB2_APB] =3D + KONA_CLK(slave, uartb2_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB3_APB] =3D + KONA_CLK(slave, uartb3_apb, bus), + [BCM281XX_SLAVE_CCU_UARTB4_APB] =3D + KONA_CLK(slave, uartb4_apb, bus), + [BCM281XX_SLAVE_CCU_SSP0_APB] =3D + KONA_CLK(slave, ssp0_apb, bus), + [BCM281XX_SLAVE_CCU_SSP2_APB] =3D + KONA_CLK(slave, ssp2_apb, bus), + [BCM281XX_SLAVE_CCU_BSC1_APB] =3D + KONA_CLK(slave, bsc1_apb, bus), + [BCM281XX_SLAVE_CCU_BSC2_APB] =3D + KONA_CLK(slave, bsc2_apb, bus), + [BCM281XX_SLAVE_CCU_BSC3_APB] =3D + KONA_CLK(slave, bsc3_apb, bus), + [BCM281XX_SLAVE_CCU_PWM_APB] =3D + KONA_CLK(slave, pwm_apb, bus), [BCM281XX_SLAVE_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; --=20 2.51.0