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[83.21.75.22]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63a5c32249esm8729019a12.41.2025.10.13.06.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 06:42:05 -0700 (PDT) From: Artur Weber Date: Mon, 13 Oct 2025 15:41:53 +0200 Subject: [PATCH v7 6/7] clk: bcm21664: Add corresponding bus clocks for peripheral clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-kona-bus-clock-v7-6-8f473d99ae19@gmail.com> References: <20251013-kona-bus-clock-v7-0-8f473d99ae19@gmail.com> In-Reply-To: <20251013-kona-bus-clock-v7-0-8f473d99ae19@gmail.com> To: Michael Turquette , Stephen Boyd , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alex Elder , Stanislav Jakubek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, phone-devel@vger.kernel.org, Artur Weber X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5074; i=aweber.kernel@gmail.com; h=from:subject:message-id; bh=UvckdDHCIlUvhCo514yvPszt5ku8/k2a2D+TilE2a7o=; b=owEBbQKS/ZANAwAKAbO7+KEToFFoAcsmYgBo7QGgr5uUByjojIQJxP+Z4YZm92iUq2cPgfNyg QKlWr3LN0eJAjMEAAEKAB0WIQTmYwAOrB3szWrSiQ2zu/ihE6BRaAUCaO0BoAAKCRCzu/ihE6BR aEmBEACKgfsKSr42+oPEwgv1AHLiKQJuBWHTC+Kzq0rE8JTwfUjCQNLZoKIJ2/JdiaqV7/CKa7Q xESb+Ey2IHBUDjRv5yZY84EYfKi4JFQQPYKZL++VeEV0v+Tg1zka6Nz5TQlPKKv7NCxMRnqIZLl 3osc4ORjN/CLC71rfrxnYzSlBWGG1h3epBtn9Goiesrgdwif3D6Fk9XB8EIgr0/VgYdU9o4DnEp CES8FQtlvPV0YpPy58OK+ra9KClBkksk7WgOZFfUl7QrGSI/WLXDyTvLfuFBHF3dxZZee2AkNGg 59J2xaBms/g4iC+Jh9RIW+E0aUvyKCA230AlnYRXP1nppVJADhDtvfO18yyA4UxJHHD+LdQukdT naj617ObLIPKVWfRyA2SSCnhW2sUEA7Bq5WXnRzxOv3n16g0Wvls3kAhn1vKJnbUxpjTRqZ0EOg wPDxwb9Bdd4JT7ZHhzQ+aoxb8aO31tccbBtPO90f7J8CFpGRN0Ka2IrxE5+QgUEAWjPLjVIwCPl /uxo6tVmO7jGszkzn6mc3NXTLCIf+7QDT8SYPtRExYQjn0/Wl0RNUiAV2B3kdHXqWWGTF5JChrE bhd8AZf6o1iQ7LP4B6q4JA0WLIM3M/we11AlUJwrYYxl2UniQpWe3Und8/Y+RugOLIKJcAsvJjm CDAgLWNlXNS8FDA== X-Developer-Key: i=aweber.kernel@gmail.com; a=openpgp; fpr=E663000EAC1DECCD6AD2890DB3BBF8A113A05168 Now that bus clock support has been implemented into the Broadcom Kona clock driver, add bus clocks corresponding to HUB_TIMER, SDIO, UART and BSC, as well as the USB OTG bus clock. Reviewed-by: Florian Fainelli Signed-off-by: Artur Weber --- Changes in v4: - Adapt to CLOCK_COUNT -> CLK_COUNT rename - Change commit summary to match equivalent BCM281xx commit Changes in v3: - Adapt to CLOCK_COUNT defines being moved Changes in v2: - Adapt to dropped prereq clocks --- drivers/clk/bcm/clk-bcm21664.c | 89 ++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm21664.c b/drivers/clk/bcm/clk-bcm21664.c index 14b7db824704..4223ac1c35a2 100644 --- a/drivers/clk/bcm/clk-bcm21664.c +++ b/drivers/clk/bcm/clk-bcm21664.c @@ -41,7 +41,12 @@ static struct peri_clk_data hub_timer_data =3D { .trig =3D TRIGGER(0x0a40, 4), }; =20 -#define BCM21664_AON_CCU_CLK_COUNT (BCM21664_AON_CCU_HUB_TIMER + 1) +static struct bus_clk_data hub_timer_apb_data =3D { + .gate =3D HW_SW_GATE(0x0414, 18, 3, 2), + .hyst =3D HYST(0x0414, 10, 11), +}; + +#define BCM21664_AON_CCU_CLK_COUNT (BCM21664_AON_CCU_HUB_TIMER_APB + 1) =20 static struct ccu_data aon_ccu_data =3D { BCM21664_CCU_COMMON(aon, AON), @@ -52,6 +57,8 @@ static struct ccu_data aon_ccu_data =3D { .kona_clks =3D { [BCM21664_AON_CCU_HUB_TIMER] =3D KONA_CLK(aon, hub_timer, peri), + [BCM21664_AON_CCU_HUB_TIMER_APB] =3D + KONA_CLK(aon, hub_timer_apb, bus), [BCM21664_AON_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; @@ -126,7 +133,27 @@ static struct peri_clk_data sdio4_sleep_data =3D { .gate =3D HW_SW_GATE(0x0360, 18, 2, 3), }; =20 -#define BCM21664_MASTER_CCU_CLK_COUNT (BCM21664_MASTER_CCU_SDIO4_SLEEP + 1) +static struct bus_clk_data sdio1_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0358, 16, 0, 1), +}; + +static struct bus_clk_data sdio2_ahb_data =3D { + .gate =3D HW_SW_GATE(0x035c, 16, 0, 1), +}; + +static struct bus_clk_data sdio3_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0364, 16, 0, 1), +}; + +static struct bus_clk_data sdio4_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0360, 16, 0, 1), +}; + +static struct bus_clk_data usb_otg_ahb_data =3D { + .gate =3D HW_SW_GATE(0x0348, 16, 0, 1), +}; + +#define BCM21664_MASTER_CCU_CLK_COUNT (BCM21664_MASTER_CCU_USB_OTG_AHB + 1) =20 static struct ccu_data master_ccu_data =3D { BCM21664_CCU_COMMON(master, MASTER), @@ -151,6 +178,16 @@ static struct ccu_data master_ccu_data =3D { KONA_CLK(master, sdio3_sleep, peri), [BCM21664_MASTER_CCU_SDIO4_SLEEP] =3D KONA_CLK(master, sdio4_sleep, peri), + [BCM21664_MASTER_CCU_SDIO1_AHB] =3D + KONA_CLK(master, sdio1_ahb, bus), + [BCM21664_MASTER_CCU_SDIO2_AHB] =3D + KONA_CLK(master, sdio2_ahb, bus), + [BCM21664_MASTER_CCU_SDIO3_AHB] =3D + KONA_CLK(master, sdio3_ahb, bus), + [BCM21664_MASTER_CCU_SDIO4_AHB] =3D + KONA_CLK(master, sdio4_ahb, bus), + [BCM21664_MASTER_CCU_USB_OTG_AHB] =3D + KONA_CLK(master, usb_otg_ahb, bus), [BCM21664_MASTER_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; @@ -231,7 +268,39 @@ static struct peri_clk_data bsc4_data =3D { .trig =3D TRIGGER(0x0afc, 19), }; =20 -#define BCM21664_SLAVE_CCU_CLK_COUNT (BCM21664_SLAVE_CCU_BSC4 + 1) +static struct bus_clk_data uartb_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0400, 16, 0, 1), +}; + +static struct bus_clk_data uartb2_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0404, 16, 0, 1), +}; + +static struct bus_clk_data uartb3_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0408, 16, 0, 1), +}; + +static struct bus_clk_data bsc1_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0458, 16, 0, 1), + .hyst =3D HYST(0x0458, 8, 9), +}; + +static struct bus_clk_data bsc2_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x045c, 16, 0, 1), + .hyst =3D HYST(0x045c, 8, 9), +}; + +static struct bus_clk_data bsc3_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0470, 16, 0, 1), + .hyst =3D HYST(0x0470, 8, 9), +}; + +static struct bus_clk_data bsc4_apb_data =3D { + .gate =3D HW_SW_GATE_AUTO(0x0474, 16, 0, 1), + .hyst =3D HYST(0x0474, 8, 9), +}; + +#define BCM21664_SLAVE_CCU_CLK_COUNT (BCM21664_SLAVE_CCU_BSC4_APB + 1) =20 static struct ccu_data slave_ccu_data =3D { BCM21664_CCU_COMMON(slave, SLAVE), @@ -254,6 +323,20 @@ static struct ccu_data slave_ccu_data =3D { KONA_CLK(slave, bsc3, peri), [BCM21664_SLAVE_CCU_BSC4] =3D KONA_CLK(slave, bsc4, peri), + [BCM21664_SLAVE_CCU_UARTB_APB] =3D + KONA_CLK(slave, uartb_apb, bus), + [BCM21664_SLAVE_CCU_UARTB2_APB] =3D + KONA_CLK(slave, uartb2_apb, bus), + [BCM21664_SLAVE_CCU_UARTB3_APB] =3D + KONA_CLK(slave, uartb3_apb, bus), + [BCM21664_SLAVE_CCU_BSC1_APB] =3D + KONA_CLK(slave, bsc1_apb, bus), + [BCM21664_SLAVE_CCU_BSC2_APB] =3D + KONA_CLK(slave, bsc2_apb, bus), + [BCM21664_SLAVE_CCU_BSC3_APB] =3D + KONA_CLK(slave, bsc3_apb, bus), + [BCM21664_SLAVE_CCU_BSC4_APB] =3D + KONA_CLK(slave, bsc4_apb, bus), [BCM21664_SLAVE_CCU_CLK_COUNT] =3D LAST_KONA_CLK, }, }; --=20 2.51.0