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X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 06:25:21.9936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4819f53-b4c8-44b1-4332-08de0a2149bf X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Postix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028CFF.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3P195MB0928 imx8mp-phyboard-pollux had a display baked into its board dts file. However this approach does not truly discribe the hardware and is not suitable when using different displays. Move display specific description into an overlay and add the successor display for the phyboard-pollux as an additional overlay. Reviewed-by: Teresa Remmet Reviewed-by: Peng Fan Signed-off-by: Yannic Moog --- arch/arm64/boot/dts/freescale/Makefile | 6 +++ .../imx8mp-phyboard-pollux-etml1010g3dra.dtso | 44 +++++++++++++++++++ .../imx8mp-phyboard-pollux-ph128800t006.dtso | 45 ++++++++++++++++++= ++ .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 49 +++++-------------= ---- 4 files changed, 105 insertions(+), 39 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 23535ed47631ca8f9db65bec5c07b6a7a7e36525..805ab9e5942bc9e2b9776e92412= f56e969b6b39a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -218,7 +218,13 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-enc-carrier-board.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk.dtb +imx8mp-phyboard-pollux-etml1010g3dra-dtbs +=3D imx8mp-phyboard-pollux-rdk.= dtb \ + imx8mp-phyboard-pollux-etml1010g3dra.dtbo +imx8mp-phyboard-pollux-ph128800t006-dtbs +=3D imx8mp-phyboard-pollux-rdk.d= tb \ + imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb= imx8mp-phycore-no-eth.dtbo +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-etml1010g3dra.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-hdmi.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g= 3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3= dra.dtso new file mode 100644 index 0000000000000000000000000000000000000000..7a7f27d6bb1be6364cbab5d2fe4= 5a365c7680fa8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dt= so @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm3 0 50000 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 =3D 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates =3D <0>, <506800000>; + status =3D "okay"; +}; + +&panel_lvds1 { + compatible =3D "edt,etml1010g3dra"; + status =3D "okay"; +}; + +&pwm3 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t= 006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t00= 6.dtso new file mode 100644 index 0000000000000000000000000000000000000000..a39f83bf820490cf946849413cc= 968f9b0a86c96 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm3 0 66667 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 =3D 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates =3D <0>, <465500000>; + status =3D "okay"; +}; + + +&panel_lvds1 { + compatible =3D "powertip,ph128800t006-zhc01"; + status =3D "okay"; +}; + +&pwm3 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b= /arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index e97d1d7c629b7fc4b52931868e35cb2d98434513..9687b4ded8f4c98fe68bcbeedcb= 5ea03434e27a3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -7,7 +7,6 @@ =20 #include #include -#include #include #include "imx8mp-phycore-som.dtsi" =20 @@ -20,16 +19,12 @@ chosen { stdout-path =3D &uart1; }; =20 - backlight_lvds: backlight { + backlight_lvds1: backlight1 { compatible =3D "pwm-backlight"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_lvds1>; - brightness-levels =3D <0 4 8 16 32 64 128 255>; - default-brightness-level =3D <11>; - enable-gpios =3D <&gpio2 20 GPIO_ACTIVE_LOW>; - num-interpolated-steps =3D <2>; + pinctrl-names =3D "default"; power-supply =3D <®_lvds1_reg_en>; - pwms =3D <&pwm3 0 50000 0>; + status =3D "disabled"; }; =20 fan0: fan { @@ -42,10 +37,11 @@ fan0: fan { #cooling-cells =3D <2>; }; =20 - panel1_lvds: panel-lvds { - compatible =3D "edt,etml1010g3dra"; - backlight =3D <&backlight_lvds>; + panel_lvds1: panel-lvds1 { + /* compatible panel in overlay */ + backlight =3D <&backlight_lvds1>; power-supply =3D <®_vcc_3v3_sw>; + status =3D "disabled"; =20 port { panel1_in: endpoint { @@ -231,32 +227,8 @@ led-3 { }; }; =20 -&lcdif2 { - status =3D "okay"; -}; - -&lvds_bridge { - status =3D "okay"; - - ports { - port@2 { - ldb_lvds_ch1: endpoint { - remote-endpoint =3D <&panel1_in>; - }; - }; - }; -}; - -&media_blk_ctrl { - /* - * The LVDS panel on this device uses 72.4 MHz pixel clock, - * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 =3D 506.8 MHz so the LDB - * serializer and LCDIFv3 scanout engine can reach accurate - * pixel clock of exactly 72.4 MHz. - */ - assigned-clock-rates =3D <500000000>, <200000000>, - <0>, <0>, <500000000>, - <506800000>; +&ldb_lvds_ch1 { + remote-endpoint =3D <&panel1_in>; }; =20 &snvs_pwrkey { @@ -281,9 +253,8 @@ &pcie { }; =20 &pwm3 { - status =3D "okay"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pwm3>; + pinctrl-names =3D "default"; }; =20 &rv3028 { --=20 2.43.0