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Mon, 13 Oct 2025 13:51:42 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:30 +0100 Subject: [PATCH 1/9] dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-1-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add dedicated compatibles for gs101 hsi0 and misc sysreg controllers to the documentation. Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) Reviewed-by: Andr=C3=A9 Draszik --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 4 = ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index d8b302f975474a87e4886006cf0b21cf758e4479..289406fb586e1a8a9eccb8eb781= f159fd5b9d6eb 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -15,7 +15,9 @@ properties: - items: - enum: - google,gs101-apm-sysreg + - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg + - google,gs101-misc-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos2200-cmgp-sysreg @@ -83,7 +85,9 @@ allOf: compatible: contains: enum: + - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg + - google,gs101-misc-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg --=20 2.51.0.760.g7b8bcc2412-goog From nobody Mon Apr 6 11:52:05 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0197B2F0C48 for ; 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Mon, 13 Oct 2025 13:51:46 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.67.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3e3206sm133512615e9.4.2025.10.13.13.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 13:51:45 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:31 +0100 Subject: [PATCH 2/9] dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-2-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Update the bindings documentation so that all CMUs (with the exception of gs101-cmu-top) have samsung,sysreg as a required property. Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) --- .../bindings/clock/google,gs101-clock.yaml | 23 ++++++++++++++++++= +++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index caf442ead24bda57e531420d8a7d8de8713032ae..5cfe98d9ba895d5207fffc82f3f= d55b602b4a2bb 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -49,6 +49,11 @@ properties: reg: maxItems: 1 =20 + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system registers interface. + required: - compatible - "#clock-cells" @@ -163,6 +168,22 @@ allOf: - const: bus - const: ip =20 + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-apm + - google,gs101-cmu-misc + - google,gs101-hsi0 + - google,gs101-cmu-hsi2 + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + required: + - samsung,sysreg + additionalProperties: false =20 examples: @@ -172,7 +193,7 @@ examples: =20 cmu_top: clock-controller@1e080000 { compatible =3D "google,gs101-cmu-top"; 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Mon, 13 Oct 2025 13:51:47 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:32 +0100 Subject: [PATCH 3/9] arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-3-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add syscon DT node for the hsi0 and misc sysreg controllers. These will be referenced by their respective CMU nodes in future patchs. Signed-off-by: Peter Griffin Reviewed-by: Andr=C3=A9 Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 31c99526470d0bb946d498f7546e70c84ed4845b..d1e3226da6472bb9db766926100= a6b9855d7a30c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -295,6 +295,12 @@ cmu_misc: clock-controller@10010000 { clock-names =3D "bus", "sss"; }; =20 + sysreg_misc: syscon@10030000 { + compatible =3D "google,gs101-misc-sysreg", "syscon"; + reg =3D <0x10030000 0x10000>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_SYSREG_MISC_PCLK>; + }; + timer@10050000 { compatible =3D "google,gs101-mct", "samsung,exynos4210-mct"; @@ -1277,6 +1283,12 @@ cmu_hsi0: clock-controller@11000000 { "usbdpdbg"; }; =20 + sysreg_hsi0: syscon@11020000 { + compatible =3D "google,gs101-hsi0-sysreg", "syscon"; + reg =3D <0x11020000 0x10000>; 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Mon, 13 Oct 2025 13:51:49 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:33 +0100 Subject: [PATCH 4/9] arm64: dts: exynos: gs101: fix clock module unit reg sizes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-4-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA The memory map lists each clock module unit as having a size of 0x10000. Additionally there are some undocumented registers in this region that need to be used for automatic clock gating mode. Some of those registers also need to be saved/restored on suspend & resume. Fixes: 86124c76683e ("arm64: dts: exynos: gs101: enable cmu-hsi2 clock cont= roller") Fixes: 4982a4a2092e ("arm64: dts: exynos: gs101: enable cmu-hsi0 clock cont= roller") Fixes: 7d66d98b5bf3 ("arm64: dts: exynos: gs101: enable cmu-peric1 clock co= ntroller") Fixes: e62c706f3aa0 ("arm64: dts: exynos: gs101: enable cmu-peric0 clock co= ntroller") Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 = SoC support") Signed-off-by: Peter Griffin Reviewed-by: Andr=C3=A9 Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d1e3226da6472bb9db766926100a6b9855d7a30c..1ae965e456665bf05aa1b08269b= 5dd66b46d200b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -288,7 +288,7 @@ soc: soc@0 { =20 cmu_misc: clock-controller@10010000 { compatible =3D "google,gs101-cmu-misc"; - reg =3D <0x10010000 0x8000>; + reg =3D <0x10010000 0x10000>; #clock-cells =3D <1>; clocks =3D <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; @@ -371,7 +371,7 @@ ppi_cluster2: interrupt-partition-2 { =20 cmu_peric0: clock-controller@10800000 { compatible =3D "google,gs101-cmu-peric0"; - reg =3D <0x10800000 0x4000>; + reg =3D <0x10800000 0x10000>; #clock-cells =3D <1>; clocks =3D <&ext_24_5m>, <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, @@ -917,7 +917,7 @@ spi_14: spi@10a20000 { =20 cmu_peric1: clock-controller@10c00000 { compatible =3D "google,gs101-cmu-peric1"; - reg =3D <0x10c00000 0x4000>; + reg =3D <0x10c00000 0x10000>; #clock-cells =3D <1>; clocks =3D <&ext_24_5m>, <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, @@ -1271,7 +1271,7 @@ spi_13: spi@10d60000 { =20 cmu_hsi0: clock-controller@11000000 { compatible =3D "google,gs101-cmu-hsi0"; - reg =3D <0x11000000 0x4000>; + reg =3D <0x11000000 0x10000>; #clock-cells =3D <1>; =20 clocks =3D <&ext_24_5m>, @@ -1344,7 +1344,7 @@ pinctrl_hsi1: pinctrl@11840000 { =20 cmu_hsi2: clock-controller@14400000 { compatible =3D "google,gs101-cmu-hsi2"; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Both the start address and size are incorrect for the apm_sysreg DT node. Update to match the TRM (rather than how it was defined downstream). Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 = SoC support") Signed-off-by: Peter Griffin Reviewed-by: Andr=C3=A9 Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 1ae965e456665bf05aa1b08269b5dd66b46d200b..ab66c055e0ac157f89a0e034f15= bbe84e20a7e82 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1414,9 +1414,9 @@ cmu_apm: clock-controller@17400000 { clock-names =3D "oscclk"; }; =20 - sysreg_apm: syscon@174204e0 { + sysreg_apm: syscon@17420000 { compatible =3D "google,gs101-apm-sysreg", "syscon"; - reg =3D <0x174204e0 0x1000>; + reg =3D <0x17420000 0x10000>; }; =20 pmu_system_controller: system-controller@17460000 { --=20 2.51.0.760.g7b8bcc2412-goog From nobody Mon Apr 6 11:52:05 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8682C309F08 for ; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Each CMU (with the exception of cmu_top) should have a phandle to its simarlarly named sysreg controller. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index ab66c055e0ac157f89a0e034f15bbe84e20a7e82..c54468ddbb02b170ec79d56ba24= 60f2ffb0dc40d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -293,6 +293,7 @@ cmu_misc: clock-controller@10010000 { clocks =3D <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names =3D "bus", "sss"; + samsung,sysreg =3D <&sysreg_misc>; }; =20 sysreg_misc: syscon@10030000 { @@ -377,6 +378,7 @@ cmu_peric0: clock-controller@10800000 { <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric0>; }; =20 sysreg_peric0: syscon@10820000 { @@ -923,6 +925,7 @@ cmu_peric1: clock-controller@10c00000 { <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; clock-names =3D "oscclk", "bus", "ip"; + samsung,sysreg =3D <&sysreg_peric1>; }; =20 sysreg_peric1: syscon@10c20000 { @@ -1281,6 +1284,7 @@ cmu_hsi0: clock-controller@11000000 { <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; clock-names =3D "oscclk", "bus", "dpgtc", "usb31drd", "usbdpdbg"; + samsung,sysreg =3D <&sysreg_hsi0>; }; =20 sysreg_hsi0: syscon@11020000 { @@ -1352,6 +1356,7 @@ cmu_hsi2: clock-controller@14400000 { <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; clock-names =3D "oscclk", "bus", "pcie", "ufs", "mmc"; + samsung,sysreg =3D <&sysreg_hsi2>; }; =20 sysreg_hsi2: syscon@14420000 { @@ -1412,6 +1417,7 @@ cmu_apm: clock-controller@17400000 { =20 clocks =3D <&ext_24_5m>; clock-names =3D "oscclk"; + samsung,sysreg =3D <&sysreg_apm>; }; =20 sysreg_apm: syscon@17420000 { --=20 2.51.0.760.g7b8bcc2412-goog From nobody Mon Apr 6 11:52:05 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1684730AACC for ; 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Mon, 13 Oct 2025 13:51:58 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.67.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3e3206sm133512615e9.4.2025.10.13.13.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 13:51:57 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:36 +0100 Subject: [PATCH 7/9] clk: samsung: Implement automatic clock gating mode for CMUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-7-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Update exynos_arm64_init_clocks() so that it enables the automatic clock mode bits in the CMU option register if the auto_clock_gate flag and option_offset fields are set for the CMU. The CMU option register bits are global and effect every clock component in the CMU, as such clearing the GATE_ENABLE_HWACG bit and setting GATE_MANUAL bit on every gate register is only required if auto_clock_gate is false. Additionally if auto_clock_gate is enabled the dynamic root clock gating and memclk registers will be configured in the corresponding CMUs sysreg bank. These registers are exposed via syscon, so the register suspend/resume paths are updated to handle using a regmap. As many gates for various Samsung SoCs are already exposed in the Samsung clock drivers a new samsung_auto_clk_gate_ops is implemented. This uses some CMU debug registers to report whether clocks are enabled or disabled when operating in automatic mode. This allows /sys/kernel/debug/clk/clk_summary to still dump the entire clock tree and correctly report the status of each clock in the system. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-exynos-arm64.c | 47 +++++++-- drivers/clk/samsung/clk-exynos4.c | 6 +- drivers/clk/samsung/clk-exynos4412-isp.c | 4 +- drivers/clk/samsung/clk-exynos5250.c | 2 +- drivers/clk/samsung/clk-exynos5420.c | 4 +- drivers/clk/samsung/clk.c | 161 +++++++++++++++++++++++++++= +--- drivers/clk/samsung/clk.h | 49 +++++++++- 7 files changed, 244 insertions(+), 29 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/c= lk-exynos-arm64.c index bf7de21f329ec89069dcf817ca578fcf9b2d9809..c302c836e8f9f6270753d86d7d9= 86c88e6762f4f 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -24,6 +24,16 @@ #define GATE_MANUAL BIT(20) #define GATE_ENABLE_HWACG BIT(28) =20 +/* Option register bits */ +#define OPT_EN_DBG BIT(31) +#define OPT_UNKNOWN BIT(30) +#define OPT_EN_PWR_MANAGEMENT BIT(29) +#define OPT_EN_AUTO_GATING BIT(28) +#define OPT_EN_MEM_PM_GATING BIT(24) + +#define CMU_OPT_GLOBAL_EN_AUTO_GATING (OPT_EN_DBG | OPT_UNKNOWN | \ + OPT_EN_PWR_MANAGEMENT | OPT_EN_AUTO_GATING | OPT_EN_MEM_PM_GATING) + /* PLL_CONx_PLL register offsets range */ #define PLL_CON_OFF_START 0x100 #define PLL_CON_OFF_END 0x600 @@ -37,6 +47,8 @@ struct exynos_arm64_cmu_data { unsigned int nr_clk_save; const struct samsung_clk_reg_dump *clk_suspend; unsigned int nr_clk_suspend; + struct samsung_clk_reg_dump *clk_sysreg_save; + unsigned int nr_clk_sysreg; =20 struct clk *clk; struct clk **pclks; @@ -82,13 +94,28 @@ static void __init exynos_arm64_init_clocks(struct devi= ce_node *np, if (!reg_base) panic("%s: failed to map registers\n", __func__); =20 + if (cmu->auto_clock_gate && cmu->option_offset) { + /* + * Enable the global automatic mode for the entire CMU. + * This overrides the individual HWACG bits in each of the + * individual gate, mux and qch registers. + */ + writel(CMU_OPT_GLOBAL_EN_AUTO_GATING, + reg_base + cmu->option_offset); + } + for (i =3D 0; i < reg_offs_len; ++i) { void __iomem *reg =3D reg_base + reg_offs[i]; u32 val; =20 if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { writel(PLL_CON1_MANUAL, reg); - } else if (is_gate_reg(reg_offs[i])) { + } else if (is_gate_reg(reg_offs[i]) && !cmu->auto_clock_gate) { + /* + * Setting GATE_MANUAL bit (which is described in TRM as + * reserved!) overrides the global CMU automatic mode + * option. + */ val =3D readl(reg); val |=3D GATE_MANUAL; val &=3D ~GATE_ENABLE_HWACG; @@ -219,7 +246,7 @@ void __init exynos_arm64_register_cmu(struct device *de= v, * Return: 0 on success, or negative error code on error. */ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev, - bool set_manual) + bool init_clk_regs) { const struct samsung_cmu_info *cmu; struct device *dev =3D &pdev->dev; @@ -249,7 +276,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform= _device *pdev, dev_err(dev, "%s: could not enable bus clock %s; err =3D %d\n", __func__, cmu->clk_name, ret); =20 - if (set_manual) + if (init_clk_regs) exynos_arm64_init_clocks(np, cmu); =20 reg_base =3D devm_platform_ioremap_resource(pdev, 0); @@ -280,14 +307,18 @@ int exynos_arm64_cmu_suspend(struct device *dev) struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); int i; =20 - samsung_clk_save(data->ctx->reg_base, data->clk_save, + samsung_clk_save(data->ctx->reg_base, NULL, data->clk_save, data->nr_clk_save); =20 + if (data->ctx->sysreg) + samsung_clk_save(NULL, data->ctx->sysreg, data->clk_save, + data->nr_clk_save); + for (i =3D 0; i < data->nr_pclks; i++) clk_prepare_enable(data->pclks[i]); =20 /* For suspend some registers have to be set to certain values */ - samsung_clk_restore(data->ctx->reg_base, data->clk_suspend, + samsung_clk_restore(data->ctx->reg_base, NULL, data->clk_suspend, data->nr_clk_suspend); =20 for (i =3D 0; i < data->nr_pclks; i++) @@ -308,9 +339,13 @@ int exynos_arm64_cmu_resume(struct device *dev) for (i =3D 0; i < data->nr_pclks; i++) clk_prepare_enable(data->pclks[i]); =20 - samsung_clk_restore(data->ctx->reg_base, data->clk_save, + samsung_clk_restore(data->ctx->reg_base, NULL, data->clk_save, data->nr_clk_save); =20 + if (data->ctx->sysreg) + samsung_clk_restore(NULL, data->ctx->sysreg, data->clk_save, + data->nr_clk_save); + for (i =3D 0; i < data->nr_pclks; i++) clk_disable_unprepare(data->pclks[i]); =20 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-ex= ynos4.c index cc5c1644c41c08b27bc48d809a08cd8a006cbe8f..26ac9734722d1e7ed8ec3f1c0a9= 56f26e32b92d4 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1378,15 +1378,15 @@ static void __init exynos4_clk_init(struct device_n= ode *np, if (soc =3D=3D EXYNOS4212 || soc =3D=3D EXYNOS4412) exynos4x12_core_down_clock(); =20 - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); if (exynos4_soc =3D=3D EXYNOS4210) - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); else - samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, + samsung_clk_sleep_init(reg_base, NULL, exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); =20 samsung_clk_of_add_provider(np, ctx); diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung= /clk-exynos4412-isp.c index fa915057e109e0008ebe0b1b5d1652fd5804e82b..772bc18a1e686f23b11bf160b80= 3becff6279637 100644 --- a/drivers/clk/samsung/clk-exynos4412-isp.c +++ b/drivers/clk/samsung/clk-exynos4412-isp.c @@ -94,7 +94,7 @@ static int __maybe_unused exynos4x12_isp_clk_suspend(stru= ct device *dev) { struct samsung_clk_provider *ctx =3D dev_get_drvdata(dev); =20 - samsung_clk_save(ctx->reg_base, exynos4x12_save_isp, + samsung_clk_save(ctx->reg_base, NULL, exynos4x12_save_isp, ARRAY_SIZE(exynos4x12_clk_isp_save)); return 0; } @@ -103,7 +103,7 @@ static int __maybe_unused exynos4x12_isp_clk_resume(str= uct device *dev) { struct samsung_clk_provider *ctx =3D dev_get_drvdata(dev); =20 - samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp, + samsung_clk_restore(ctx->reg_base, NULL, exynos4x12_save_isp, ARRAY_SIZE(exynos4x12_clk_isp_save)); return 0; } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk= -exynos5250.c index e90d3a0848cbc24b2709c10795f6affcda404567..f97f30b29be7317db8186bac39c= f52e1893eb106 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -854,7 +854,7 @@ static void __init exynos5250_clk_init(struct device_no= de *np) PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); __raw_writel(tmp, reg_base + PWR_CTRL2); =20 - samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs)); exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus), exynos5250_subcmus); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk= -exynos5420.c index a9df4e6db82fa7831d4e5c7210b0163d7d301ec1..1982e0751ceec7e57f9e82d96dc= badce1f691092 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1649,12 +1649,12 @@ static void __init exynos5x_clk_init(struct device_= node *np, ARRAY_SIZE(exynos5800_cpu_clks)); } =20 - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); =20 if (soc =3D=3D EXYNOS5800) { - samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, + samsung_clk_sleep_init(reg_base, NULL, exynos5800_clk_regs, ARRAY_SIZE(exynos5800_clk_regs)); =20 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index dbc9925ca8f46e951dfb5d391c0e744ca370abcc..07b2948ae7ea48f126ab420be57= d8c2705979464 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include =20 #include "clk.h" @@ -21,19 +23,29 @@ static LIST_HEAD(clock_reg_cache_list); =20 void samsung_clk_save(void __iomem *base, + struct regmap *regmap, struct samsung_clk_reg_dump *rd, unsigned int num_regs) { - for (; num_regs > 0; --num_regs, ++rd) - rd->value =3D readl(base + rd->offset); + for (; num_regs > 0; --num_regs, ++rd) { + if (base) + rd->value =3D readl(base + rd->offset); + if (regmap) + regmap_read(regmap, rd->offset, &rd->value); + } } =20 void samsung_clk_restore(void __iomem *base, + struct regmap *regmap, const struct samsung_clk_reg_dump *rd, unsigned int num_regs) { - for (; num_regs > 0; --num_regs, ++rd) - writel(rd->value, base + rd->offset); + for (; num_regs > 0; --num_regs, ++rd) { + if (base) + writel(rd->value, base + rd->offset); + if (regmap) + regmap_write(regmap, rd->offset, rd->value); + } } =20 struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( @@ -227,6 +239,82 @@ void __init samsung_clk_register_div(struct samsung_cl= k_provider *ctx, } } =20 +#define ACG_MSK GENMASK(6, 4) +#define CLK_IDLE GENMASK(5, 4) +static int samsung_auto_clk_gate_is_en(struct clk_hw *hw) +{ + u32 reg; + struct clk_gate *gate =3D to_clk_gate(hw); + + reg =3D readl(gate->reg); + return ((reg & ACG_MSK) =3D=3D CLK_IDLE) ? 0 : 1; +} + +/* enable and disable are nops in automatic clock mode */ +static int samsung_auto_clk_gate_en(struct clk_hw *hw) +{ + return 0; +} + +static void samsung_auto_clk_gate_dis(struct clk_hw *hw) +{ +} + +static const struct clk_ops samsung_auto_clk_gate_ops =3D { + .enable =3D samsung_auto_clk_gate_en, + .disable =3D samsung_auto_clk_gate_dis, + .is_enabled =3D samsung_auto_clk_gate_is_en, +}; + +struct clk_hw *samsung_register_auto_gate(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_gate *gate; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret =3D -EINVAL; + + /* allocate the gate */ + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &samsung_auto_clk_gate_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_gate assignments */ + gate->reg =3D reg; + gate->bit_idx =3D bit_idx; + gate->flags =3D clk_gate_flags; + gate->lock =3D lock; + gate->hw.init =3D &init; + + hw =3D &gate->hw; + if (dev || !np) + ret =3D clk_hw_register(dev, hw); + else if (np) + ret =3D of_clk_hw_register(np, hw); + if (ret) { + kfree(gate); + hw =3D ERR_PTR(ret); + } + + return hw; +} + /* register a list of gate clocks */ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, const struct samsung_gate_clock *list, @@ -234,11 +322,21 @@ void __init samsung_clk_register_gate(struct samsung_= clk_provider *ctx, { struct clk_hw *clk_hw; unsigned int idx; + void __iomem *reg_offs; =20 for (idx =3D 0; idx < nr_clk; idx++, list++) { - clk_hw =3D clk_hw_register_gate(ctx->dev, list->name, list->parent_name, - list->flags, ctx->reg_base + list->offset, + reg_offs =3D ctx->reg_base + list->offset; + + if (ctx->auto_clock_gate && ctx->gate_dbg_offset) + clk_hw =3D samsung_register_auto_gate(ctx->dev, NULL, + list->name, list->parent_name, NULL, NULL, + list->flags, reg_offs + ctx->gate_dbg_offset, list->bit_idx, list->gate_flags, &ctx->lock); + else + clk_hw =3D clk_hw_register_gate(ctx->dev, list->name, + list->parent_name, list->flags, + ctx->reg_base + list->offset, list->bit_idx, + list->gate_flags, &ctx->lock); if (IS_ERR(clk_hw)) { pr_err("%s: failed to register clock %s\n", __func__, list->name); @@ -276,10 +374,11 @@ static int samsung_clk_suspend(void) struct samsung_clock_reg_cache *reg_cache; =20 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) { - samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, - reg_cache->rd_num); - samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend, - reg_cache->rsuspend_num); + samsung_clk_save(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rdump, reg_cache->rd_num); + samsung_clk_restore(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rsuspend, + reg_cache->rsuspend_num); } return 0; } @@ -289,8 +388,8 @@ static void samsung_clk_resume(void) struct samsung_clock_reg_cache *reg_cache; =20 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) - samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump, - reg_cache->rd_num); + samsung_clk_restore(reg_cache->reg_base, reg_cache->sysreg, + reg_cache->rdump, reg_cache->rd_num); } =20 static struct syscore_ops samsung_clk_syscore_ops =3D { @@ -299,6 +398,7 @@ static struct syscore_ops samsung_clk_syscore_ops =3D { }; =20 void samsung_clk_extended_sleep_init(void __iomem *reg_base, + struct regmap *sysreg, const unsigned long *rdump, unsigned long nr_rdump, const struct samsung_clk_reg_dump *rsuspend, @@ -319,6 +419,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_= base, register_syscore_ops(&samsung_clk_syscore_ops); =20 reg_cache->reg_base =3D reg_base; + reg_cache->sysreg =3D sysreg; reg_cache->rd_num =3D nr_rdump; reg_cache->rsuspend =3D rsuspend; reg_cache->rsuspend_num =3D nr_rsuspend; @@ -334,6 +435,12 @@ void samsung_clk_extended_sleep_init(void __iomem *reg= _base, void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx, const struct samsung_cmu_info *cmu) { + ctx->auto_clock_gate =3D cmu->auto_clock_gate; + ctx->gate_dbg_offset =3D cmu->gate_dbg_offset; + ctx->option_offset =3D cmu->option_offset; + ctx->drcg_offset =3D cmu->drcg_offset; + ctx->memclk_offset =3D cmu->memclk_offset; + if (cmu->pll_clks) samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks); if (cmu->mux_clks) @@ -353,6 +460,31 @@ void __init samsung_cmu_register_clocks(struct samsung= _clk_provider *ctx, samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks); } =20 +/* Enable Dynamic Root Clock Gating of bus components*/ +void samsung_en_dyn_root_clk_gating(struct device_node *np, + struct samsung_clk_provider *ctx, + const struct samsung_cmu_info *cmu) +{ + if (ctx && !ctx->auto_clock_gate) + return; + + ctx->sysreg =3D syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); + if (!IS_ERR_OR_NULL(ctx->sysreg)) { + regmap_write(ctx->sysreg, ctx->drcg_offset, 0xffffffff); + /* not every sysreg controller has memclk reg*/ + if (ctx->memclk_offset) + regmap_write_bits(ctx->sysreg, ctx->memclk_offset, 0x1, 0x0); + + samsung_clk_extended_sleep_init(NULL, ctx->sysreg, + cmu->sysreg_clk_regs, + cmu->nr_sysreg_clk_regs, + NULL, 0); + } else { + pr_warn("%pOF: Unable to get CMU sysreg\n", np); + ctx->sysreg =3D NULL; + } +} + /* * Common function which registers plls, muxes, dividers and gates * for each CMU. It also add CMU register list to register cache. @@ -374,11 +506,14 @@ struct samsung_clk_provider * __init samsung_cmu_regi= ster_one( samsung_cmu_register_clocks(ctx, cmu); =20 if (cmu->clk_regs) - samsung_clk_extended_sleep_init(reg_base, + samsung_clk_extended_sleep_init(reg_base, NULL, cmu->clk_regs, cmu->nr_clk_regs, cmu->suspend_regs, cmu->nr_suspend_regs); =20 samsung_clk_of_add_provider(np, ctx); =20 + /* sysreg DT nodes reference a clock in this CMU */ + samsung_en_dyn_root_clk_gating(np, ctx, cmu); + return ctx; } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 18660c1ac6f0106b17b9efc9c6b3cd62d46f7b82..b719e057f45489e9d92ba54031f= e633a8c9264ce 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -12,6 +12,7 @@ =20 #include #include +#include #include "clk-pll.h" #include "clk-cpu.h" =20 @@ -19,13 +20,25 @@ * struct samsung_clk_provider - information about clock provider * @reg_base: virtual address for the register base * @dev: clock provider device needed for runtime PM + * @sysreg: syscon regmap for clock-provider sysreg controller * @lock: maintains exclusion between callbacks for a given clock-provider + * @auto_clock_gate: enable auto clk mode for all clocks in clock-provider + * @gate_dbg_offset: gate debug reg offset. Used for all gates in auto clk= mode + * @option_offset: option reg offset. Enables auto mode for clock-provider + * @drcg_offset: dynamic root clk gate enable register offset + * @memclk_offset: memclk enable register offset * @clk_data: holds clock related data like clk_hw* and number of clocks */ struct samsung_clk_provider { void __iomem *reg_base; struct device *dev; + struct regmap *sysreg; spinlock_t lock; + bool auto_clock_gate; + u32 gate_dbg_offset; + u32 option_offset; + u32 drcg_offset; + u32 memclk_offset; /* clk_data must be the last entry due to variable length 'hws' array */ struct clk_hw_onecell_data clk_data; }; @@ -310,6 +323,7 @@ struct samsung_cpu_clock { struct samsung_clock_reg_cache { struct list_head node; void __iomem *reg_base; + struct regmap *sysreg; struct samsung_clk_reg_dump *rdump; unsigned int rd_num; const struct samsung_clk_reg_dump *rsuspend; @@ -338,7 +352,14 @@ struct samsung_clock_reg_cache { * @suspend_regs: list of clock registers to set before suspend * @nr_suspend_regs: count of clock registers in @suspend_regs * @clk_name: name of the parent clock needed for CMU register access + * @sysreg_clk_regs: list of sysreg clock registers + * @nr_sysreg_clk_regs: count of clock registers in @sysreg_clk_regs * @manual_plls: Enable manual control for PLL clocks + * @auto_clock_gate: enable auto clock mode for all components in CMU + * @gate_dbg_offset: gate debug reg offset. Used by all gates in auto clk = mode + * @option_offset: option reg offset. Enables auto clk mode for entire CMU + * @drcg_offset: dynamic root clk gate enable register offset + * @memclk_offset: memclk enable register offset */ struct samsung_cmu_info { const struct samsung_pll_clock *pll_clks; @@ -364,8 +385,16 @@ struct samsung_cmu_info { unsigned int nr_suspend_regs; const char *clk_name; =20 + const unsigned long *sysreg_clk_regs; + unsigned int nr_sysreg_clk_regs; + /* ARM64 Exynos CMUs */ bool manual_plls; + bool auto_clock_gate; + u32 gate_dbg_offset; + u32 option_offset; + u32 drcg_offset; + u32 memclk_offset; }; =20 struct samsung_clk_provider *samsung_clk_init(struct device *dev, @@ -415,6 +444,7 @@ struct samsung_clk_provider *samsung_cmu_register_one( =20 #ifdef CONFIG_PM_SLEEP void samsung_clk_extended_sleep_init(void __iomem *reg_base, + struct regmap *sysreg, const unsigned long *rdump, unsigned long nr_rdump, const struct samsung_clk_reg_dump *rsuspend, @@ -426,17 +456,32 @@ static inline void samsung_clk_extended_sleep_init(vo= id __iomem *reg_base, const struct samsung_clk_reg_dump *rsuspend, unsigned long nr_rsuspend) {} #endif -#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \ - samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0) +#define samsung_clk_sleep_init(reg_base, sysreg, rdump, nr_rdump) \ + samsung_clk_extended_sleep_init(reg_base, sysreg, rdump, nr_rdump, \ + NULL, 0) =20 void samsung_clk_save(void __iomem *base, + struct regmap *regmap, struct samsung_clk_reg_dump *rd, unsigned int num_regs); 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable auto clock mode, and define the additional fields which are used when this mode is enabled. /sys/kernel/debug/clk/clk_summary now reports approximately 308 running clocks and 298 disabled clocks. Prior to this commit 586 clocks were running and 17 disabled. To ensure compatability with older DTs the resource size is checked and an error issued if the DT needs updating. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 80 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 80 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 70b26db9b95ad0b376d23f637c7683fbc8c8c600..baf41ae6c9e2480cb83531acf7e= ae190c6aff819 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include @@ -17,6 +18,8 @@ #include "clk-exynos-arm64.h" #include "clk-pll.h" =20 +int check_cmu_res_size(struct device_node *np); + /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) @@ -26,6 +29,10 @@ #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) =20 +#define GS101_GATE_DBG_OFFSET 0x4000 +#define GS101_DRCG_EN_OFFSET 0x104 +#define GS101_MEMCLK_OFFSET 0x108 + /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_TOP (0x1e080000) */ @@ -1433,6 +1440,9 @@ static const struct samsung_cmu_info top_cmu_info __i= nitconst =3D { .nr_clk_ids =3D CLKS_NR_TOP, .clk_regs =3D cmu_top_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_top_clk_regs), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D CMU_CMU_TOP_CONTROLLER_OPTION, }; =20 static void __init gs101_cmu_top_init(struct device_node *np) @@ -1900,6 +1910,11 @@ static const struct samsung_gate_clock apm_gate_clks= [] __initconst =3D { CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_C= RITICAL, 0), }; =20 +static const unsigned long dcrg_memclk_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, + GS101_MEMCLK_OFFSET, +}; + static const struct samsung_cmu_info apm_cmu_info __initconst =3D { .mux_clks =3D apm_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(apm_mux_clks), @@ -1912,6 +1927,12 @@ static const struct samsung_cmu_info apm_cmu_info __= initconst =3D { .nr_clk_ids =3D CLKS_NR_APM, .clk_regs =3D apm_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(apm_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI0 ---------------------------------------------------------= --- */ @@ -2375,7 +2396,14 @@ static const struct samsung_cmu_info hsi0_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI0, .clk_regs =3D hsi0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(hsi0_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI0_CMU_HSI0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_HSI2 ---------------------------------------------------------= --- */ @@ -2863,7 +2891,14 @@ static const struct samsung_cmu_info hsi2_cmu_info _= _initconst =3D { .nr_clk_ids =3D CLKS_NR_HSI2, .clk_regs =3D cmu_hsi2_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_hsi2_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D HSI2_CMU_HSI2_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 /* ---- CMU_MISC ---------------------------------------------------------= --- */ @@ -3423,11 +3458,37 @@ static const struct samsung_cmu_info misc_cmu_info = __initconst =3D { .nr_clk_ids =3D CLKS_NR_MISC, .clk_regs =3D misc_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(misc_clk_regs), + .sysreg_clk_regs =3D dcrg_memclk_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D MISC_CMU_MISC_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, + .memclk_offset =3D GS101_MEMCLK_OFFSET, }; =20 +/* for old DT compatbility with incorrect CMU size*/ +int check_cmu_res_size(struct device_node *np) +{ + struct resource res; + resource_size_t size; + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + size =3D resource_size(&res); + if (size !=3D 0x10000) { + pr_warn("%pOF: resource to small. Please update your DT\n", np); + return -ENODEV; + } + return 0; +} + static void __init gs101_cmu_misc_init(struct device_node *np) { + if (check_cmu_res_size(np)) + return; exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); } =20 @@ -4010,6 +4071,10 @@ static const struct samsung_gate_clock peric0_gate_c= lks[] __initconst =3D { 21, 0, 0), }; =20 +static const unsigned long dcrg_sysreg[] __initconst =3D { + GS101_DRCG_EN_OFFSET, +}; + static const struct samsung_cmu_info peric0_cmu_info __initconst =3D { .mux_clks =3D peric0_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(peric0_mux_clks), @@ -4020,7 +4085,13 @@ static const struct samsung_cmu_info peric0_cmu_info= __initconst =3D { .nr_clk_ids =3D CLKS_NR_PERIC0, .clk_regs =3D peric0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric0_clk_regs), + .sysreg_clk_regs =3D dcrg_sysreg, + .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_sysreg), .clk_name =3D "bus", + .auto_clock_gate =3D true, + .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, + .option_offset =3D PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + .drcg_offset =3D GS101_DRCG_EN_OFFSET, }; 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Mon, 13 Oct 2025 13:52:03 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.67.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3e3206sm133512615e9.4.2025.10.13.13.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 13:52:01 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:38 +0100 Subject: [PATCH 9/9] clk: samsung: gs101: remove CLK_IGNORE_UNUSED and CLK_IS_CRITICAL flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251013-automatic-clocks-v1-9-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Now each CMU is in automatic mode these flags are no longer necessary. All unused clocks are automatically gated & ungated by hardware as required. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 87 +++++++++++++++++--------------------= ---- 1 file changed, 35 insertions(+), 52 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index baf41ae6c9e2480cb83531acf7eae190c6aff819..d01c94994d86bc27d344969c339= 55da63ed0e4a1 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -1901,13 +1901,13 @@ static const struct samsung_gate_clock apm_gate_clk= s[] __initconst =3D { CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_C= RITICAL, 0), GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, "gout_apm_uasc_p_apm_pclk", "gout_apm_func", - CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_C= RITICAL, 0), + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_APM_WDT_APM_PCLK, "gout_apm_wdt_apm_pclk", "gout_apm_func", CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", - CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_C= RITICAL, 0), + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), }; =20 static const unsigned long dcrg_memclk_sysreg[] __initconst =3D { @@ -2211,11 +2211,10 @@ static const struct samsung_div_clock hsi0_div_clks= [] __initconst =3D { }; =20 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst =3D { - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_PCLK, "gout_hsi0_hsi0_pclk", "mout_hsi0_bus", CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26, "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26", "mout_hsi0_usb20_ref", @@ -2252,16 +2251,14 @@ static const struct samsung_gate_clock hsi0_gate_cl= ks[] __initconst =3D { "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK, "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK, "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK, "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, @@ -2286,21 +2283,18 @@ static const struct samsung_gate_clock hsi0_gate_cl= ks[] __initconst =3D { "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK, "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK, "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2, "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK, "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, @@ -2358,21 +2352,18 @@ static const struct samsung_gate_clock hsi0_gate_cl= ks[] __initconst =3D { "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB= _PCLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK, "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK, "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK, "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), }; =20 static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst= =3D { @@ -2677,22 +2668,19 @@ static const struct samsung_gate_clock hsi2_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK, "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21, - CLK_IGNORE_UNUSED, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + 0, 0), GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK, "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK, "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK, "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK, "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, @@ -2795,38 +2783,35 @@ static const struct samsung_gate_clock hsi2_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK, "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK, "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK, "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK, "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk", CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK, "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK, "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2, "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK, "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK, "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, @@ -2862,25 +2847,23 @@ static const struct samsung_gate_clock hsi2_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK, "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO, "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK, "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, - 21, CLK_IS_CRITICAL, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK, "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK, "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), }; =20 static const struct samsung_cmu_info hsi2_cmu_info __initconst =3D { @@ -3849,7 +3832,7 @@ static const struct samsung_gate_clock peric0_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, "gout_peric0_clk_peric0_oscclk_clk", "oscclk", CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_= CLK, @@ -3865,12 +3848,12 @@ static const struct samsung_gate_clock peric0_gate_= clks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, @@ -4003,7 +3986,7 @@ static const struct samsung_gate_clock peric0_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, @@ -4012,7 +3995,7 @@ static const struct samsung_gate_clock peric0_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, @@ -4310,7 +4293,7 @@ static const struct samsung_gate_clock peric1_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC1_PCLK, "gout_peric1_peric1_pclk", "mout_peric1_bus_user", CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, @@ -4330,11 +4313,11 @@ static const struct samsung_gate_clock peric1_gate_= clks[] __initconst =3D { GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, --=20 2.51.0.760.g7b8bcc2412-goog