From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5362A29AB1A; Mon, 13 Oct 2025 17:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377668; cv=none; b=iA71DIVMYDN5N0MGjh07+qEAfNKcqx1+I1gw8wUZ+nXthtIGSzYpUBtOVkJH1R4J41y9gulgHcGVEe6R3CDu9b8CzYcJQSDVeJtRRp/n5fvs8R5+6lgrkOyO8yi0zxWtn1oBveL6WCHS7kZRNxymbKollJ9XKi48idCNDIv/Gyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377668; c=relaxed/simple; bh=LlxOX0XdXGOPt3oDaTbfcdhtJfrWKo6DQBQFWyQqX78=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aPEzwTV4myWknh/M+jZ5BDLMTvUL9TQUd+4H2qwsGeeyDgQUJWUlca1Np6G5iKD5yN1usJTZlM3q89u6p1+c77Es4S50D61pn2L3Vld5GZmgapbUhgddkL5I7ArnYxDpHLbiuX9NOVFKywpF+1/8jFTUkNO3h5sliJ02+z5jZ5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s5G6GReD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s5G6GReD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5C78C116B1; Mon, 13 Oct 2025 17:47:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377667; bh=LlxOX0XdXGOPt3oDaTbfcdhtJfrWKo6DQBQFWyQqX78=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s5G6GReDfu7EobXs19mLrzGPdFL55sM1gsACHZxoUUTdSZTbp7IhPh9idUciZ7Wf+ hbb4KrgLBny0irXbzF3sbFDUWcGAEaP+NXMeni0ky4HAkCjJWK3vlXKuEoiJtH5/TX jOLGVS7R1ActZlJ6xVyLbRCd5Ys/5Z+UZqWc7bvYOq1zHubd92XXGA5zJfXV1Kvj3H N8EcwGKsTtpInSM2RF0BNrCjILCVOI7O2ZVZdaziFL8VGaMq7dkoTfPz0j1JMigQbw eip5P4w9bTYX5LBRFwuWYjVJ/jRejhw6DZcyFWRLjOEFoQoaaV8pKDnVgRPFnIxjSG i5W5+cIUbtGxA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Date: Mon, 13 Oct 2025 18:45:33 +0100 Message-ID: <20251013-posting-alright-8f945a4bebfd@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2941; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=W/92o0rvdQPG7KvXPwubOldJUAMEfyDDSsE844RVnYI=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrfbr6kyrsTRy3z7FrEv6xe399bPylN4G3Vl9LeDJK Zn1MaaaHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIlzcjw2wOw/ZlG19HOXIb ZZ+IvPE5V/LeBo68+vybpz9ydITWVjEyvHonNFNGKuzWdWeD94uCVjs85Dv10f1g3ULhxfU/Oj3 9eAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley "mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a= 4fefe@wendy/ [1] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- v3: - drop simple-mfd at Krzysztof's request since the child nodes do not yet exist. v2: - clean up various minor comments from Rob on mpfs-mss-top-sysreg - remove mpfs-control-scb from this patch --- .../microchip,mpfs-mss-top-sysreg.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 000000000000..1ab691db8795 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + reg =3D <0x20002000 0x1000>; + #reset-cells =3D <1>; + }; + --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FE7C28000B; Mon, 13 Oct 2025 17:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377671; cv=none; b=c8BPFZ+RB+7GDM9lLv/mT+yjoLHHsfLbkzaVYzQSlS95t7SFD2raM4kyVypdDmh0DDz2hGJokqGAUmj3/qzXNX8J5r8l1cZOMECh6LlfBaxqJQexbRjvjOKt9FtFABt0+OBTSZ3W+GRu4onBUjhOv4EdE5N06/gs7MWHh4BvmdA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377671; c=relaxed/simple; bh=LLvPaeaDgbN1v+SEvOddhb8/ImHBKYgsCBzaGq5fKtA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mrvdUEg6254s+M8Zypuqc3Ua4hLzTeDeX413FzbHTSM7+EaMp0f5LOkPB5DGZDZvqqHAKuum+Ykf2SO41plVJKnHnn8Fu9g/hM3Th5QuF2a6nbt2qy0soc+Co+aZ51pXH59RuspNbUHpetEdDaDsBGL1XeciDlNnKJxnatqDDQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h0JwQ+84; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h0JwQ+84" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B8AAC116C6; Mon, 13 Oct 2025 17:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377671; bh=LLvPaeaDgbN1v+SEvOddhb8/ImHBKYgsCBzaGq5fKtA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h0JwQ+84uewBHrXs9AI4/ypHaJbeDEwnizotdzk6OnMnmWjSUbqGFwXpaFFCk1gcC epFf6J+sEHv7nRQq/UOVQ5jFQ1tL3s6xsuBDRUYBd2B3MYB0o4EQc/OacNOucI6pec ZYzWmzpIF3Ki/UfgczQTzZw3BUFLMz7IEZgeTuj+IR1cONMdbS6O/n15Yf1Z6TgHeg b9I0ahl7f96w1wjyx5y0ydM14P2y728ChzZbmFLRwAL5WvBtxsknBHMLLXKkyoUquq Ku7T/19s9Lga9cxD4mio/+zlvtYgBmToCiyHPlVnN48P0hotYCsqE4SPABBtXBOedF 3SxLHe774FEnA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/9] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC Date: Mon, 13 Oct 2025 18:45:34 +0100 Message-ID: <20251013-patient-matrimony-6162c8f92e2e@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4873; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Lcc0lHBfQVQLXEUPw6TwgGGxT3tWaxaoKaJLIXpLxZk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrfYHrq+Tdn3saNaw9g6fxLxbz3ZPiGgM1VZb0tN5T mql2NTIjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzE/CnDP60js/m5VB3yCm7I /dz79ablA8ZN5/K13l8qXZTD96ykSI2RYbccs9Ir4d0l3/ImnN7ok8HifMQkaeWuyxanpTZKBef 4MAIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The control-scb and mss-top-sysreg regions on PolarFire SoC both fulfill multiple purposes. The former is used for mailbox functions in addition to the temperature & voltage sensor while the latter is used for clocks, resets, interrupt muxing and pinctrl. Signed-off-by: Conor Dooley --- drivers/soc/microchip/Kconfig | 13 ++++++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-control-scb.c | 45 +++++++++++++++++++ drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 +++++++++++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 drivers/soc/microchip/mpfs-control-scb.c create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index 19f4b576f822..31d188311e05 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -9,3 +9,16 @@ config POLARFIRE_SOC_SYS_CTRL module will be called mpfs_system_controller. =20 If unsure, say N. + +config POLARFIRE_SOC_SYSCONS + bool "PolarFire SoC (MPFS) syscon drivers" + default y + depends on ARCH_MICROCHIP + select MFD_CORE + help + These drivers add support for the syscons on PolarFire SoC (MPFS). + Without these drivers core parts of the kernel such as clocks + and resets will not function correctly. + + If unsure, and on a PolarFire SoC, say y. + diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile index 14489919fe4b..1a3a1594b089 100644 --- a/drivers/soc/microchip/Makefile +++ b/drivers/soc/microchip/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) +=3D mpfs-sys-controller.o +obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) +=3D mpfs-control-scb.o mpfs-mss-top-s= ysreg.o diff --git a/drivers/soc/microchip/mpfs-control-scb.c b/drivers/soc/microch= ip/mpfs-control-scb.c new file mode 100644 index 000000000000..d1a8e79c232e --- /dev/null +++ b/drivers/soc/microchip/mpfs-control-scb.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_control_scb_devs[] =3D { + { .name =3D "mpfs-tvs", }, +}; + +static int mpfs_control_scb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs, + 1, NULL, 0, NULL); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id mpfs_control_scb_of_match[] =3D { + {.compatible =3D "microchip,mpfs-control-scb", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_control_scb_of_match); + +static struct platform_driver mpfs_control_scb_driver =3D { + .driver =3D { + .name =3D "mpfs-control-scb", + .of_match_table =3D mpfs_control_scb_of_match, + }, + .probe =3D mpfs_control_scb_probe, +}; +module_platform_driver(mpfs_control_scb_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC control scb driver"); diff --git a/drivers/soc/microchip/mpfs-mss-top-sysreg.c b/drivers/soc/micr= ochip/mpfs-mss-top-sysreg.c new file mode 100644 index 000000000000..9b2e7b84cdba --- /dev/null +++ b/drivers/soc/microchip/mpfs-mss-top-sysreg.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_mss_top_sysreg_devs[] =3D { + { .name =3D "mpfs-reset", }, +}; + +static int mpfs_mss_top_sysreg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_dev= s, + 1, NULL, 0, NULL); + if (ret) + return ret; + + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children\n"); + + return 0; +} + +static const struct of_device_id mpfs_mss_top_sysreg_of_match[] =3D { + {.compatible =3D "microchip,mpfs-mss-top-sysreg", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mss_top_sysreg_of_match); + +static struct platform_driver mpfs_mss_top_sysreg_driver =3D { + .driver =3D { + .name =3D "mpfs-mss-top-sysreg", + .of_match_table =3D mpfs_mss_top_sysreg_of_match, + }, + .probe =3D mpfs_mss_top_sysreg_probe, +}; +module_platform_driver(mpfs_mss_top_sysreg_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver"); --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F65C28E571; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fCDCoNa5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CA9AC4CEE7; Mon, 13 Oct 2025 17:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377674; bh=gYIW6qM4II8bzUyw/0Yitdmt2pkZmG4mm0A5gjVISyQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fCDCoNa5eT+TgBGOQfI6f13AjT85WIkf0+Gyb28RA3CP0XMSxKW63uFqspFNqhPQJ khNDIJpZfNLI+d40S/fMC6QDhnTWGaftOUCKvYhd56/O6YWVmj4D9bx0nxcFZDVLQ6 uO9tQYZ1GrJIQbRQQ8jKLSApWOq6ekuVjkNc0FNideiMbkPiYMa1sUpwtSBNw77Ac4 ka+sjBU900kKOB6swJZ/0EF6Sua+YrB8wpJLgLYpRmFDgYdhkjh0DCc2nMSvNUsNvE jKniEtq9w8C+rhXyl91cReH+LTYmz41mpWBb4Fu23+t4MFf406gFnXCByL66H399Ci WMfVThZUxG37g== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing Date: Mon, 13 Oct 2025 18:45:35 +0100 Message-ID: <20251013-crane-utilize-cff9298291a4@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6170; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=atjxMOlwn8gZYomggzeS9HhyZYxGjL5gzEklClKSlp8=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ5I7E75yDx359215zusHKcUl5gfXbMxXVNcUdrxt oLMv6/8HaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjI5VsMf8Uj3h6/zizrWlL1 wXzuiS8RFknskXt2fm++V6az7vFBFyaGv0JL3F/Z7dn44P0k1c4Z2au6KpkSbRe7tl6RSPMWWbd rDy8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- v4: - Only use driver specific lock for non-regmap writes v2: - Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/reset/reset-mpfs.c | 83 ++++++++++++++++++++++++++++++-------- 1 file changed, 66 insertions(+), 17 deletions(-) diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index f6fa10e03ea8..8e5ed4deecf3 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,13 +7,16 @@ * */ #include +#include #include #include +#include #include #include #include -#include +#include #include +#include #include #include =20 @@ -27,11 +30,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +52,50 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), BIT(id)); + return 0; + } + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg |=3D BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), 0); + return 0; + } + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg &=3D ~BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +145,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +194,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -176,12 +225,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0DAD299AAA; Mon, 13 Oct 2025 17:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377678; cv=none; b=KWfpc4VX1/gFEU725UMOH6dqSGxOCmTXRACqnNj+1vEutHpiRpcDtu8qrqzNFDpgZIB4NxLRSNeFvA3zHc4cIDO7aFtpJkaxfbZuNt2y1faCmKjkFzS5S8WefRp+B3EsyOlzEdALM4mxJxpG0om9rkDOVxq2Ir6p8Oe2b8JuOnY= ARC-Message-Signature: i=1; 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b=AqZ4NnGyMwYhSkM/nSuGxuHjq3fWTwzsRZxzEyVAUVhf9arf3dX/y6hC7v55UTF5/ 8EsYK8utRcv2vv5zjNkr4kg1ityxzfF5eux69k3PptY0a2fk3jY1S+ZQ3dBjBSRde7 YDJSovrhifkZDI4fEmBh5GyamWrPownKJXbXkhbNn8J4AxVBCjzqrlGCilBtENHYR5 +/TNWXuqLE2t0FLbauoZ7X0qGej56BKtoLzHfb+u6Mkjdda/p8IUSpIUcGXMYSmVn0 Q2GPxgjBKbIM2CwH3aHN2Gz6UIHcW0/zFTEoUQ2jDPVO2aIAkr6eNX3vhtG6fLFZ97 irluD7npJEZXA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/9] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Mon, 13 Oct 2025 18:45:36 +0100 Message-ID: <20251013-spectacle-slacks-86d498db7d60@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3159; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=3LZvSpbfmHa0zvD2pQSWl0P8VI7zypG9G9PgJJXjfzU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ40OHiq/XJ44fGo0PM9q3nZyUUtCnWhFbYigYf0T 5ydo+TTUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIlsPc7wP8n12/yfjmH/LMvn X+Eyr7b7Gz/7RkbvB9PTE79E1OQaODL8r4h2/b99eXvC0RIbw+ffza/EtM/559PxxucvR9mmA0t 72AE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2..ee4f31596d97 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A56F2C3254; Mon, 13 Oct 2025 17:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377681; cv=none; b=gWgHkp8uwWTIJcIlkW6cJDbhvVUA2WPX8HPuAL/+bFBNdEyPxEGfBz3FHjR9dg9yhbU7LjYESPRm1lA0DOijziVFX9DBzJFQBtvZIp+8Jw5N8LE8yf3Lg82WmQJ5a1K7Tty33lLuJHwDICdZ/2qWQE99Wc6iNXPOTllL5w+e0Uw= ARC-Message-Signature: i=1; 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b=qzy1Iyfng5jJSuQu7buDtUiKcPA7x5nhEm3E7c0SiPqI/WKxlTu5knzPj1VRoq7YU JJUMu3u9bjp+EOLaoczSwswP1zdidBWSo/qNpJ0Ooz6y9IPuOebbzk9yXqcMoQ7HYd aPs1RoJLZuTU4teT+dasqSMQdap2wlc7y2UXaw5Mg+7X7RtbGKBeCc+PwzC0ytuHas rDFBazujNmEVAesEnXDkOkAe/AX19YmewOzQY1B4ZSq+orOs5PRAzLytEw/wx0ls3F GI0UF27ixhK/2d3aOG6Ol+CsoXka9Ebw11SGqb6XpAk2UZFGYQ1P498Vpd5hNSLv1e 6hYbnK3NxSLiA== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks Date: Mon, 13 Oct 2025 18:45:37 +0100 Message-ID: <20251013-undercook-flatfoot-70dca974cd19@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12719; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=tKeSiWQ6AV92c0bFuS+NXSiRQH403qtpuI89XqsoORk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ5YMp+a6HR+YZ0OfzxH974/X7aKWE7omN/kv/WfT faNx6cWdpSyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiu9wZGWa9npSyP2Fe2IKp jbJcUZzsFlde3IrQ4ZHiXrN06+5D6yYz/M9LdzmiYmgjJ/vFO7PM9dNp9Rs1SvsTHLSfreatf+d cxwQA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmaps instead of iomem addresses as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. This is effectively a revert of commit 4da2404bb003 ("clk: microchip: mpfs: convert cfg_clk to clk_divider") and commit d815569783e6 ("clk: microchip: mpfs: convert periph_clk to clk_gate") as it resurrects the ops structures removed in those commits, with the readl()s and writel()s replaced by regmap_read()s and regmap_writes()s. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 2 + drivers/clk/microchip/clk-mpfs.c | 250 ++++++++++++++++++++++++++----- 2 files changed, 211 insertions(+), 41 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 0724ce65898f..1b9e43eb5497 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -7,6 +7,8 @@ config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST default ARCH_MICROCHIP_POLARFIRE + depends on MFD_SYSCON select AUXILIARY_BUS + select REGMAP_MMIO help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index c22632a7439c..e3362be9b266 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -6,8 +6,10 @@ */ #include #include +#include #include #include +#include #include #include =20 @@ -30,6 +32,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config mpfs_clk_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +49,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -67,18 +78,37 @@ struct mpfs_msspll_out_hw_clock { =20 #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 +struct mpfs_cfg_clock { + struct regmap *map; + const struct clk_div_table *table; + u8 map_offset; + u8 shift; + u8 width; + u8 flags; +}; + struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct mpfs_cfg_clock cfg; + struct clk_hw hw; unsigned int id; - u32 reg_offset; +}; + +#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, h= w) + +struct mpfs_periph_clock { + struct regmap *map; + u8 map_offset; + u8 shift; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct mpfs_periph_clock periph; + struct clk_hw hw; unsigned int id; }; =20 +#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_cl= ock, hw) + /* * mpfs_clk_lock prevents anything else from writing to the * mpfs clk block while a software locked register is being written. @@ -219,16 +249,66 @@ static int mpfs_clk_register_msspll_outs(struct devic= e *dev, /* * "CFG" clocks */ +static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned = long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + u32 val; =20 -#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ - .id =3D _id, \ - .cfg.shift =3D _shift, \ - .cfg.width =3D _width, \ - .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ - .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ + regmap_read(cfg->map, cfg->map_offset, &val); + val >>=3D cfg->shift; + val &=3D clk_div_mask(cfg->width); + + return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->w= idth); +} + +static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate,= unsigned long *prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + + return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); +} + +static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, un= signed long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw =3D to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg =3D &cfg_hw->cfg; + unsigned long flags; + u32 val; + int divider_setting; + + divider_setting =3D divider_get_val(rate, prate, cfg->table, cfg->width, = 0); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + regmap_read(cfg->map, cfg->map_offset, &val); + val &=3D ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); + val |=3D divider_setting << cfg->shift; + regmap_write(cfg->map, cfg->map_offset, val); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + +static const struct clk_ops mpfs_clk_cfg_ops =3D { + .recalc_rate =3D mpfs_cfg_clk_recalc_rate, + .round_rate =3D mpfs_cfg_clk_round_rate, + .set_rate =3D mpfs_cfg_clk_set_rate, +}; + +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ + .id =3D _id, \ + .cfg.shift =3D _shift, \ + .cfg.width =3D _width, \ + .cfg.table =3D _table, \ + .cfg.map_offset =3D _offset, \ + .cfg.flags =3D _flags, \ + .hw.init =3D CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } =20 #define CLK_CPU_OFFSET 0u @@ -248,10 +328,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { .cfg.shift =3D 0, .cfg.width =3D 12, .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, + .cfg.map_offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops,= 0), } }; =20 @@ -264,14 +344,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->cfg.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &cfg_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->hw; } =20 return 0; @@ -281,15 +361,67 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ =20 -#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ +static int mpfs_periph_clk_enable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + u32 val; + unsigned long flags; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + regmap_read(periph->map, periph->map_offset, &val); + val |=3D 1u << periph->shift; + regmap_write(periph->map, periph->map_offset, val); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +static void mpfs_periph_clk_disable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + u32 val; + unsigned long flags; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + regmap_read(periph->map, periph->map_offset, &val); + val &=3D ~(1u << periph->shift); + regmap_write(periph->map, periph->map_offset, val); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); +} + +static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw =3D to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph =3D &periph_hw->periph; + u32 val; + + regmap_read(periph->map, periph->map_offset, &val); + if (val & (1u << periph->shift)) + return 1; + + return 0; +} + +static const struct clk_ops mpfs_periph_clk_ops =3D { + .enable =3D mpfs_periph_clk_enable, + .disable =3D mpfs_periph_clk_disable, + .is_enabled =3D mpfs_periph_clk_is_enabled, +}; + +#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ + .id =3D _id, \ + .periph.map_offset =3D REG_SUBBLK_CLOCK_CR, \ + .periph.shift =3D _shift, \ + .hw.init =3D CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags)= , \ +} + +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) =20 /* * Critical clocks: @@ -346,19 +478,60 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->periph.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &periph_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->hw; } =20 return 0; } =20 +static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data, + struct platform_device *pdev) +{ + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + return 0; +} + +static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_da= ta, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + ret =3D mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_R= ESET_CR); + if (ret) + return ret; + + return 0; +} + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -374,13 +547,12 @@ static int mpfs_clk_probe(struct platform_device *pde= v) if (!clk_data) return -ENOMEM; =20 - clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_data->base)) - return PTR_ERR(clk_data->base); - - clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(clk_data->msspll_base)) - return PTR_ERR(clk_data->msspll_base); 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Mon, 13 Oct 2025 17:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377683; bh=yx40n6aW+7axlHFIv+/k4z1XcQ+4QDorszZ6b/jKM44=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O1ov6qgsCC+yGKq4N9oLMRt+D9rGFNCpo4Rew9BM8xH0s0J+vdCDQPHen6LUokd+p zdNQgFL/ENzp/uEI4qGNRdP+xoJ73FZ5OO8RBGA7yD8iDStSc/b28iaV5io7o3aN4e apK4mMyE/mV5K1eI/s+3Tn6L8z6/lb3t0W8HI8lJtlCXLTPewSwJMNBacEClO5f+LY h6SLU2UGc8AlDgxeO95rf+uDNn9R2XM+nYDPOAAcO2yrzXV74plEM3maipS2xiFEbj 2szzCtlpodmJNerS047bDB4c7vRXlhhwI064vI+w1+pFYeU+C6FZKO/H+wp9tlseew 8NdLXNaZFxJNQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/9] riscv: dts: microchip: fix mailbox description Date: Mon, 13 Oct 2025 18:45:38 +0100 Message-ID: <20251013-failing-wobbly-56a7bce3f21b@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2048; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=CJ93zZ/gwT2VF26tXat2Gljwq2Roq9NVUZwBFI4dODQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ4Ebjlkd6djitCy1O23n+oLfs3xrs+9d8kwppUti Tnqy6+PHaUsDGJcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIMTmGf+aNet8uPzNZfdj6 /gZf7pSp9SmHb1/dU3n8ctKTeXfudW5gZFijeLvuTvn+VU4/XqgvCjM4PbH9zQz16W8WCBvukPq 9rJ0FAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c5..f9d6bf08e717 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 962702C0276; Mon, 13 Oct 2025 17:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377687; cv=none; b=d9fKTFX4XcLECLUdw10PLUQmE9w8SYdTTz1NgImtW64ZRBh/xShA9W6d8CD2n6S3ncz/g7Ps2DXBlh+VeiwUhyVb2kIM3CefDYapEofKYSvra5G2/s3r5Rixue3zTUlUfK7OYErs6k9ss+8KjWk7sfokyq9+gLcWqwQvVkkUeTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377687; c=relaxed/simple; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JV8jNM7Ew5xuLCHqkMJKZ4OGqMjw4Q4Us/Ifw8nhKRe7fj3nyn5hZ7SOiEZDmUN/99fzOQxUCOE5b9Pu6L3D8PaXCk7blPk4ATXdXx3ENoPKCG9OipBCmVvLov7avVZng4QFN4wlXCxkuve6LgpBA377GY22w4Fhw4kMOtsv23U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FddGmuzX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FddGmuzX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 530F3C4CEE7; Mon, 13 Oct 2025 17:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377687; bh=o06pwj8GQhduMpl8X9PMCjFDAGlLMLElJucB88tSCYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FddGmuzXEPWGJiD8edvsv5EIrfNMx2o7xlTVcAvgS7jTCf4o13YZ8QPipLTJPAKkq Jj/cavfYWjB03ykTnC7YFXWhQK9JIo1il+tXKtLK8GYj9+dFj8K12V9De2/o1Sqc4w 5tC6nwPkIZBO7c+0kqU9CzocvS9RIrXFMHV7gGIuQfD72eAsZmIc+GnqA31PpMYE1D 5mudkdoVm+atcuaoXjSOhpyr6+NXyp4X66oXGtEUanpRu2AILeXMtW/yIpH2EpIZcZ ZR6vOLUwmwfYFabONmiFmiyrPbOfrNooLGON0K2Yr4AiKAL9K0WAlqM2KYjoocmp1u xQPHtYrnI0nXQ== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 7/9] riscv: dts: microchip: convert clock and reset to use syscon Date: Mon, 13 Oct 2025 18:45:39 +0100 Message-ID: <20251013-princess-unstitch-a6a0c75f8c12@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2216; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=+zR8fbMXO9YW4YzwKnjp5SrmA8iRht4FGjwYBRXJ6yY=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ5Os7+pdNj+rW+22OWQFPdZE7l9F0tFdpWqsgvMv Ks4uSixo5SFQYyLQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABNhXsjwV/Tz0WxDEwZrjxtW X66c53vppczPcS42a8KBJY9EmWR/TGT4px2imVFxbP10rTXlNnNP6lu8+XRRZcFtg+cNH6K0NkX t5wAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e717..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4A4127A129; Mon, 13 Oct 2025 17:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 13 Oct 2025 17:48:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377690; bh=E43Z5Y8tSJqRgamwuiELwt0g0OSF4ium8fxWSOTU1R0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qujdbc16f7MiyfY0lPmh3IzN15hzoM0c3atnmpR/raocNuIMANh9SeMnOtgU0iTg1 estioe/QofSs2DoK4XPJmkXrAX5A86hkijot0EDgzQUjHCopWtGoAtpugAugArvmLG 5BIf0RQBiWlVeII843aqhbp6KQHKL8jDQN8PcURW3+RTKl4qn8DC6kGsLU/CeMUsIW MtsXm/SiQ9289Y2DzfC0itMJiEw+aY1g54cHQC8CMLheppwLxK+s8fV/2LUWibD4o/ S7pVrrr6JFH0F7PLacIWRqCEfb535DtfXlKirChMkmdcYaZ/k13r+fxbc2PZRI/ozX BNobxQsi+zuYg== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 8/9] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Date: Mon, 13 Oct 2025 18:45:40 +0100 Message-ID: <20251013-sinister-undocked-be95b8e93df8@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=733; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=gmAo0f4txEXEqIJYVzrDbfZIGVrUbtgonOlTrrMh7lQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ7OP/OqnuvG5oBDh7/oCnxc4nvkfflzdwPXPRPOx 8Y3JPYf7ShlYRDjYpAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEroQyMrw7w2M31f/CVylX HXsOm6POc604723If3T4BYfACceTsxoZ/pmbVkiVH7K5lSV2py30tULRjXlnpvZdEYtJu7Wt9Gf +CxYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the two new syscon drivers to the RISC-V entry for Microchip platforms. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..a28740a7d87a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22105,6 +22105,8 @@ F: drivers/pci/controller/plda/pcie-microchip-host.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c +F: drivers/soc/microchip/mpfs-control-scb.c +F: drivers/soc/microchip/mpfs-mss-top-sysreg.c F: drivers/soc/microchip/mpfs-sys-controller.c F: drivers/spi/spi-microchip-core-qspi.c F: drivers/spi/spi-microchip-core.c --=20 2.51.0 From nobody Fri Dec 19 15:34:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B04FF2C15A2; Mon, 13 Oct 2025 17:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377693; cv=none; b=mQUvvQpFoL7jo1R4o3GBSPfkSVjqElnDnWgwgzuVq7GYy5O124CNbX6cfAG9zbDAaoYXfZnH0GprqsebRqfGdYLNwvj2PA2KzIYH7T8qROirsM1xgVI1Xv0tvhbrONEBB/F1HqFHpmywuW6ZoTO6LSE9CsEWKI+iJvmfLLSbcAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760377693; c=relaxed/simple; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jfkQJ4XPnllmP+L9DrAPO/2b0M+93SYZhQ02/80IWBY0OQJaZx1z6BTQBwbegyfcQXiGO1LGWQaccfwXf4gDkmfmeO1XutE7/RwIEzM/miA5nBZ4kN+5L1G1ZMwd+Sc+5qJRXd9qW5Fbx1M/Puo5t47Rn24rfaJVxGBntcQh/GA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jEke+fgY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jEke+fgY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD02CC19421; Mon, 13 Oct 2025 17:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760377693; bh=4tliw4UQndH1N9g1/up84eMEVp/xYC+YCAsm2JdOf3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jEke+fgYjB1mUr/bWEFrIGcs/AqCyLZw0E7ayMz2kpPI96yMJE5HZnMvF22I5BHQ+ HvXtKAaqDDy/5VW7q3zwbN78pIS0HAJjdZngKmuxViGWUCnahZmzIfFXXgzSs2pGFQ cLPqeJMIpfwLcAb5ZVBhOiiUwOez5aBh/PcJBFIChLHOk/ip8yA+fPFKWGL4uML6YE jaYJwxOeAB/xwFIBtBVkzS9ExjXLCdKYS4eoAHBsnYFtGPeQRNCYqpYx7CnzQ9bpr1 wRaCbEBihdVk1OQj0hVY6zCqaxOX4/UFhpszImq7SkLhAYKLGpdpy5dhS8ijtRzjbj Xy1sl0jrUSK9Q== From: Conor Dooley To: claudiu.beznea@tuxon.dev Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 9/9] MAINTAINERS: rename Microchip RISC-V entry Date: Mon, 13 Oct 2025 18:45:41 +0100 Message-ID: <20251013-unwelcome-crusher-2bedb9ecb35f@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud> References: <20251013-album-bovine-faf9f5ebc5d4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=735; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=WjqbuqvJbBVUVn1s3EoLv4wSnU+jVPnRC0yZy4Sseq4=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlvrQ6y/Nq440O46HGvly8niUk2cq5knPvlxNb4/weSa l0+1/+O7ChlYRDjYpAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEHnkz/FOzPcL1ciUf5+Id 5pEn38tpNAcv+X9EqKN1X9XlEuMAcXuGfzoX+61nz7q9OC0s8F7VovQpZZktUTKdR2bvm5b90+1 GDxsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There's now non-FPGA RISC-V SoCs from Microchip, so rename the entry to reflect that. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a28740a7d87a..24efae3df425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22079,7 +22079,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/gi= t/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ =20 -RISC-V MICROCHIP FPGA SUPPORT +RISC-V MICROCHIP SUPPORT M: Conor Dooley M: Daire McNamara L: linux-riscv@lists.infradead.org --=20 2.51.0