From nobody Sun Feb 8 12:25:45 2026 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE64123D7E9 for ; Sun, 12 Oct 2025 23:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760312126; cv=none; b=NbU5A4Q05OLlPJnr92jOHQDfIWrzecELjG6o1McBwyqjmP6UK/R1SIy9gnRb4NKmvuCdtIK0SznhY9xfsY8eu9UnU8Y4K99I8Ec4+hKXbJSRtlFNznhkvoB6FRC5tgFMzJCQaF7vjUnGJaxomX8pn7RR3rtJp435CDzw3ekyGk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760312126; c=relaxed/simple; bh=gkLy2Qgcq7gN47EkW82rgH1br37FBToXcsjbZlxUg0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hd9c+MjxAQu5fKLewNA+ttBdxcRx1KSB+uTkd51sQhg3c1rttnEzlC8FrWOS+AMPghd/6LXIKT8AljeLgB7juZGhAgIAnVXv9dXKq1mEN4CPWwOpqTsbivtP9uleL8Jr/CEPVKkD3lr3JAY8y/8TadtK/oXbnFr3FhbLhv6Zpm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=D9dxE88R; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="D9dxE88R" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1760312123; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aMQxUdZpKenu9e4nFmMim5iXKBYHWVcK5NULU+g21sU=; b=D9dxE88R60fxDnkI3tHA8ApGl7LoVnog7o4mCXbJ0I6yg7FmmVNauMJuXlCWIXoboQe+SI AFqAjTmXT5bhnGP0x96VTO5FpvHNo/vsxmB4a2y56Brdb9bhQJgOH3Wg0OEG8xfCPR1AUG H2wz/tlhDlW31WPEofYF2kcee7xS+e0Yc3neKItfxuBZB0L4DhOifKNpoJ3Grcioqoyrd0 s93BbVG78dIVvjMdYUjyfBbvhWodQ8Dt43uGMwmatkckFRGoimAaeACR0082946XeCdWOc 7jHP/pQEeF2WJdnGAVa88oX9WT9hX0hEpLMUrcd+5yYIrZrIZcRB/e8yESiQBg== From: Val Packett To: Sebastian Reichel , Neil Armstrong , Fenglin Wu Cc: Val Packett , Sebastian Reichel , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] power: supply: qcom_battmgr: clamp charge control thresholds Date: Sun, 12 Oct 2025 20:32:18 -0300 Message-ID: <20251012233333.19144-3-val@packett.cool> In-Reply-To: <20251012233333.19144-2-val@packett.cool> References: <20251012233333.19144-2-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The sysfs API documentation says that drivers "round written values to the nearest supported value" for charge_control_end_threshold. Let's do this for both thresholds, as userspace (e.g. upower) generally does not expect these writes to fail at all. Fixes: cc3e883a0625 ("power: supply: qcom_battmgr: Add charge control suppo= rt") Signed-off-by: Val Packett --- drivers/power/supply/qcom_battmgr.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 3c2837ef3461..c8028606bba0 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -678,12 +678,7 @@ static int qcom_battmgr_set_charge_start_threshold(str= uct qcom_battmgr *battmgr, u32 target_soc, delta_soc; int ret; =20 - if (start_soc < CHARGE_CTRL_START_THR_MIN || - start_soc > CHARGE_CTRL_START_THR_MAX) { - dev_err(battmgr->dev, "charge control start threshold exceed range: [%u = - %u]\n", - CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_START_THR_MAX); - return -EINVAL; - } + start_soc =3D clamp(start_soc, CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_STA= RT_THR_MAX); =20 /* * If the new start threshold is larger than the old end threshold, @@ -716,12 +711,7 @@ static int qcom_battmgr_set_charge_end_threshold(struc= t qcom_battmgr *battmgr, i u32 delta_soc =3D CHARGE_CTRL_DELTA_SOC; int ret; =20 - if (end_soc < CHARGE_CTRL_END_THR_MIN || - end_soc > CHARGE_CTRL_END_THR_MAX) { - dev_err(battmgr->dev, "charge control end threshold exceed range: [%u - = %u]\n", - CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_MAX); - return -EINVAL; - } + end_soc =3D clamp(end_soc, CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_M= AX); =20 if (battmgr->info.charge_ctrl_start && end_soc > battmgr->info.charge_ctr= l_start) delta_soc =3D end_soc - battmgr->info.charge_ctrl_start; --=20 2.51.0 From nobody Sun Feb 8 12:25:45 2026 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7118C2EFDA2; Sun, 12 Oct 2025 23:35:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760312130; cv=none; b=VRlKiqXzxuoRbTTWAeh9X7Lm4r992HAYCR8ktaGZ0D4MV67yzHe4kZIlA4TwHIrlln/sk27uHXVFAWldn7AAiXl7CAfkpe7cZ4PBM6IPyTxesY2mIgLHPx7DYWdkOHQ0nBftMpdQ6sSD+h/iLApavcmboBDdAMkv2lkU1rVt1S8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760312130; c=relaxed/simple; bh=HcgvRsl6W0SNKxZG8xv51myRgFtAdDrV+t95LVLew9E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uR+sHmdXVMs42/dZBRl56NOVmEVrO5fpJKElbpnBoE0JQ41Uxqhq7ENN1DsXw0aHNYZ9fBLEmuapvTQr0t6oxtkgHLjcu2HrnCqANXQ9QeRy8KYsKx9zq6kSKIfSMrzuC8NymoryhPgdoKwSvFks2NwASCj9+WTDLHzQjcrIb0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=b/q4eQxk; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="b/q4eQxk" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1760312126; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AqflzUk4CL99JJ1fV54jyel3/p1XOOUdQirvgksUsSo=; b=b/q4eQxk/ANOiFw2WPA0ueuB18mLKM4tT6KpP1YKLLmJu02BUe5P1xL7zcggCDf1Jc5hWp XI5JhZaWLzc3nhR/UeINo22TzmEnpFTnzsUO1k/nYFtRXpNX3Sogd16adwque1ZzUo6jK9 yvHmC58EIPRXi86h9CYouE51suEXVJTcoqYJTo8dqa5emMFGtrV08qMQ0gmI6LV2aKcfxD kTvUq7BSHrkjnbM+kVMnlG8gATGyClKrIlXCdoSzbwFDg06pcaRyWdl7CDIeEhKUSDf5MV vDqxXZhM+jLR+uR+mSY8BJQ2Xk6sWKQLZ6VpArBsV8Qt53Q8Mo+si/nc0J2wLw== From: Val Packett To: Sebastian Reichel , Fenglin Wu , Neil Armstrong Cc: Val Packett , Sebastian Reichel , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] power: supply: qcom_battmgr: support disabling charge control Date: Sun, 12 Oct 2025 20:32:19 -0300 Message-ID: <20251012233333.19144-4-val@packett.cool> In-Reply-To: <20251012233333.19144-2-val@packett.cool> References: <20251012233333.19144-2-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Existing userspace (in particular, upower) disables charge control by setting the start threshold to 0 and the stop threshold to 100. Handle that by actually setting the enable bit to 0 when a start threshold of 0 was requested. Fixes: cc3e883a0625 ("power: supply: qcom_battmgr: Add charge control suppo= rt") Signed-off-by: Val Packett --- drivers/power/supply/qcom_battmgr.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index c8028606bba0..e6f01e0122e1 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -257,6 +257,7 @@ struct qcom_battmgr_info { unsigned int capacity_warning; unsigned int cycle_count; unsigned int charge_count; + bool charge_ctrl_enable; unsigned int charge_ctrl_start; unsigned int charge_ctrl_end; char model_number[BATTMGR_STRING_LEN]; @@ -659,13 +660,13 @@ static int qcom_battmgr_bat_get_property(struct power= _supply *psy, } =20 static int qcom_battmgr_set_charge_control(struct qcom_battmgr *battmgr, - u32 target_soc, u32 delta_soc) + bool enable, u32 target_soc, u32 delta_soc) { struct qcom_battmgr_charge_ctrl_request request =3D { .hdr.owner =3D cpu_to_le32(PMIC_GLINK_OWNER_BATTMGR), .hdr.type =3D cpu_to_le32(PMIC_GLINK_REQ_RESP), .hdr.opcode =3D cpu_to_le32(BATTMGR_CHG_CTRL_LIMIT_EN), - .enable =3D cpu_to_le32(1), + .enable =3D cpu_to_le32(enable), .target_soc =3D cpu_to_le32(target_soc), .delta_soc =3D cpu_to_le32(delta_soc), }; @@ -677,6 +678,7 @@ static int qcom_battmgr_set_charge_start_threshold(stru= ct qcom_battmgr *battmgr, { u32 target_soc, delta_soc; int ret; + bool enable =3D start_soc !=3D 0; =20 start_soc =3D clamp(start_soc, CHARGE_CTRL_START_THR_MIN, CHARGE_CTRL_STA= RT_THR_MAX); =20 @@ -696,9 +698,10 @@ static int qcom_battmgr_set_charge_start_threshold(str= uct qcom_battmgr *battmgr, } =20 mutex_lock(&battmgr->lock); - ret =3D qcom_battmgr_set_charge_control(battmgr, target_soc, delta_soc); + ret =3D qcom_battmgr_set_charge_control(battmgr, enable, target_soc, delt= a_soc); mutex_unlock(&battmgr->lock); if (!ret) { + battmgr->info.charge_ctrl_enable =3D enable; battmgr->info.charge_ctrl_start =3D start_soc; battmgr->info.charge_ctrl_end =3D target_soc; } @@ -710,6 +713,7 @@ static int qcom_battmgr_set_charge_end_threshold(struct= qcom_battmgr *battmgr, i { u32 delta_soc =3D CHARGE_CTRL_DELTA_SOC; int ret; + bool enable =3D battmgr->info.charge_ctrl_enable; =20 end_soc =3D clamp(end_soc, CHARGE_CTRL_END_THR_MIN, CHARGE_CTRL_END_THR_M= AX); =20 @@ -717,7 +721,7 @@ static int qcom_battmgr_set_charge_end_threshold(struct= qcom_battmgr *battmgr, i delta_soc =3D end_soc - battmgr->info.charge_ctrl_start; =20 mutex_lock(&battmgr->lock); - ret =3D qcom_battmgr_set_charge_control(battmgr, end_soc, delta_soc); + ret =3D qcom_battmgr_set_charge_control(battmgr, enable, end_soc, delta_s= oc); mutex_unlock(&battmgr->lock); if (!ret) { battmgr->info.charge_ctrl_start =3D end_soc - delta_soc; --=20 2.51.0