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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d67d8283sm760176466b.38.2025.10.12.12.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Oct 2025 12:23:47 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 07/30] drm/sun4i: Move blender config from layers to mixer Date: Sun, 12 Oct 2025 21:23:07 +0200 Message-ID: <20251012192330.6903-8-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251012192330.6903-1-jernej.skrabec@gmail.com> References: <20251012192330.6903-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With upcoming DE33 support, layer management must be decoupled from other operations like blender configuration. There are two reasons: - DE33 will have separate driver for planes and thus it will be harder to manage different register spaces - Architecturaly it's better to split access by modules. Blender is now exclusively managed by mixer. Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 17 ++++++++++++++--- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 22 +++------------------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 +++------------------- 3 files changed, 20 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index f7f210a925f8..a3194b71dc6d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -283,8 +283,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *eng= ine, =20 drm_for_each_plane(plane, state->dev) { struct sun8i_layer *layer =3D plane_to_sun8i_layer(plane); + int w, h, x, y, zpos; bool enable; - int zpos; =20 if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer !=3D = mixer) continue; @@ -295,10 +295,14 @@ static void sun8i_mixer_commit(struct sunxi_engine *e= ngine, =20 enable =3D plane_state->crtc && plane_state->visible; zpos =3D plane_state->normalized_zpos; + x =3D plane_state->dst.x1; + y =3D plane_state->dst.y1; + w =3D drm_rect_width(&plane_state->dst); + h =3D drm_rect_height(&plane_state->dst); =20 - DRM_DEBUG_DRIVER(" plane %d: chan=3D%d ovl=3D%d en=3D%d zpos=3D%d\n", + DRM_DEBUG_DRIVER(" plane %d: chan=3D%d ovl=3D%d en=3D%d zpos=3D%d x=3D%= d y=3D%d w=3D%d h=3D%d\n", plane->base.id, layer->channel, layer->overlay, - enable, zpos); + enable, zpos, x, y, w, h); =20 /* * We always update the layer enable bit, because it can clear @@ -312,6 +316,13 @@ static void sun8i_mixer_commit(struct sunxi_engine *en= gine, /* Route layer to pipe based on zpos */ route |=3D layer->channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); pipe_en |=3D SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); + + regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), + SUN8I_MIXER_COORD(x, y)); + regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), + SUN8I_MIXER_SIZE(w, h)); } =20 regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i= /sun8i_ui_layer.c index 8baa1d0b53bd..12c83c54f9bc 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -47,21 +47,17 @@ static void sun8i_ui_layer_update_alpha(struct sun8i_mi= xer *mixer, int channel, } =20 static void sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int cha= nnel, - int overlay, struct drm_plane *plane, - unsigned int zpos) + int overlay, struct drm_plane *plane) { struct drm_plane_state *state =3D plane->state; u32 src_w, src_h, dst_w, dst_h; - struct regmap *bld_regs; - u32 bld_base, ch_base; u32 outsize, insize; u32 hphase, vphase; + u32 ch_base; =20 DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n", channel, overlay); =20 - bld_base =3D sun8i_blender_base(mixer); - bld_regs =3D sun8i_blender_regmap(mixer); ch_base =3D sun8i_channel_base(mixer, channel); =20 src_w =3D drm_rect_width(&state->src) >> 16; @@ -113,17 +109,6 @@ static void sun8i_ui_layer_update_coord(struct sun8i_m= ixer *mixer, int channel, else sun8i_ui_scaler_enable(mixer, channel, false); } - - /* Set base coordinates */ - DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", - state->dst.x1, state->dst.y1); - DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); - regmap_write(bld_regs, - SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), - SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); - regmap_write(bld_regs, - SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), - outsize); } =20 static void sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int c= hannel, @@ -230,14 +215,13 @@ static void sun8i_ui_layer_atomic_update(struct drm_p= lane *plane, struct drm_plane_state *new_state =3D drm_atomic_get_new_plane_state(stat= e, plane); struct sun8i_layer *layer =3D plane_to_sun8i_layer(plane); - unsigned int zpos =3D new_state->normalized_zpos; struct sun8i_mixer *mixer =3D layer->mixer; =20 if (!new_state->crtc || !new_state->visible) return; =20 sun8i_ui_layer_update_coord(mixer, layer->channel, - layer->overlay, plane, zpos); + layer->overlay, plane); sun8i_ui_layer_update_alpha(mixer, layer->channel, layer->overlay, plane); sun8i_ui_layer_update_formats(mixer, layer->channel, diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.c index dae6f83cea6e..1f4fa63ef153 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -49,25 +49,21 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mi= xer *mixer, int channel, } =20 static void sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int cha= nnel, - int overlay, struct drm_plane *plane, - unsigned int zpos) + int overlay, struct drm_plane *plane) { struct drm_plane_state *state =3D plane->state; const struct drm_format_info *format =3D state->fb->format; u32 src_w, src_h, dst_w, dst_h; - struct regmap *bld_regs; - u32 bld_base, ch_base; u32 outsize, insize; u32 hphase, vphase; u32 hn =3D 0, hm =3D 0; u32 vn =3D 0, vm =3D 0; bool subsampled; + u32 ch_base; =20 DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n", channel, overlay); =20 - bld_base =3D sun8i_blender_base(mixer); - bld_regs =3D sun8i_blender_regmap(mixer); ch_base =3D sun8i_channel_base(mixer, channel); =20 src_w =3D drm_rect_width(&state->src) >> 16; @@ -180,17 +176,6 @@ static void sun8i_vi_layer_update_coord(struct sun8i_m= ixer *mixer, int channel, SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(vn) | SUN8I_MIXER_CHAN_VI_DS_M(vm)); - - /* Set base coordinates */ - DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", - state->dst.x1, state->dst.y1); - DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); - regmap_write(bld_regs, - SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), - SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); - regmap_write(bld_regs, - SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), - outsize); } =20 static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *forma= t) @@ -350,14 +335,13 @@ static void sun8i_vi_layer_atomic_update(struct drm_p= lane *plane, struct drm_plane_state *new_state =3D drm_atomic_get_new_plane_state(stat= e, plane); struct sun8i_layer *layer =3D plane_to_sun8i_layer(plane); - unsigned int zpos =3D new_state->normalized_zpos; struct sun8i_mixer *mixer =3D layer->mixer; =20 if (!new_state->crtc || !new_state->visible) return; =20 sun8i_vi_layer_update_coord(mixer, layer->channel, - layer->overlay, plane, zpos); + layer->overlay, plane); sun8i_vi_layer_update_alpha(mixer, layer->channel, layer->overlay, plane); sun8i_vi_layer_update_formats(mixer, layer->channel, --=20 2.51.0