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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d67d8283sm760176466b.38.2025.10.12.12.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Oct 2025 12:24:11 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 27/30] drm/sun4i: mixer: split out layer config Date: Sun, 12 Oct 2025 21:23:27 +0200 Message-ID: <20251012192330.6903-28-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251012192330.6903-1-jernej.skrabec@gmail.com> References: <20251012192330.6903-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Later special plane only driver for DE33 will provide separate configuration. This change will also help layer driver migrate away from mixer structure. Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun8i_csc.c | 2 +- drivers/gpu/drm/sun4i/sun8i_mixer.c | 152 +++++++++++++++--------- drivers/gpu/drm/sun4i/sun8i_mixer.h | 32 +++-- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 2 +- drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 2 +- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 8 +- 6 files changed, 122 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8= i_csc.c index c371e94b95bd..30779db2f9b2 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -240,7 +240,7 @@ void sun8i_csc_config(struct sun8i_layer *layer, return; } =20 - base =3D ccsc_base[layer->mixer->cfg->ccsc][layer->channel]; + base =3D ccsc_base[layer->mixer->cfg->lay_cfg.ccsc][layer->channel]; =20 sun8i_csc_setup(layer->regs, base, mode, state->color_encoding, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index f9131396f22f..a01eccfca3a9 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -703,137 +703,173 @@ static void sun8i_mixer_remove(struct platform_devi= ce *pdev) } =20 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg =3D { - .ccsc =3D CCSC_MIXER0_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 3, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg =3D { - .ccsc =3D CCSC_MIXER1_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER1_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, - .scaler_mask =3D 0x3, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 1, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg =3D { - .ccsc =3D CCSC_MIXER0_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 432000000, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 3, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg =3D { - .ccsc =3D CCSC_MIXER0_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 3, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg =3D { - .ccsc =3D CCSC_MIXER1_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER1_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0x3, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 1, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg =3D { - .de_type =3D SUN8I_MIXER_DE2, - .vi_num =3D 2, - .ui_num =3D 1, - .scaler_mask =3D 0x3, - .scanline_yuv =3D 2048, - .vi_scaler_num =3D 2, - .ccsc =3D CCSC_MIXER0_LAYOUT, - .mod_rate =3D 150000000, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .vi_scaler_num =3D 2, + }, + .de_type =3D SUN8I_MIXER_DE2, + .mod_rate =3D 150000000, + .vi_num =3D 2, + .ui_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg =3D { - .ccsc =3D CCSC_D1_MIXER0_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_D1_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0x3, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 1, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg =3D { - .ccsc =3D CCSC_MIXER1_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER1_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x1, + .scanline_yuv =3D 1024, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0x1, - .scanline_yuv =3D 1024, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 0, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg =3D { - .ccsc =3D CCSC_MIXER0_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER0_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 4096, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 4096, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 3, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg =3D { - .ccsc =3D CCSC_MIXER1_LAYOUT, + .lay_cfg =3D { + .ccsc =3D CCSC_MIXER1_LAYOUT, + .de_type =3D SUN8I_MIXER_DE2, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .de2_fcc_alpha =3D 1, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE2, .mod_rate =3D 297000000, - .scaler_mask =3D 0x3, - .scanline_yuv =3D 2048, - .de2_fcc_alpha =3D 1, - .vi_scaler_num =3D 1, .ui_num =3D 1, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg =3D { + .lay_cfg =3D { + .de_type =3D SUN8I_MIXER_DE3, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 4096, + .vi_scaler_num =3D 1, + }, .de_type =3D SUN8I_MIXER_DE3, .mod_rate =3D 600000000, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 4096, - .vi_scaler_num =3D 1, .ui_num =3D 3, .vi_num =3D 1, }; =20 static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg =3D { + .lay_cfg =3D { + .de_type =3D SUN8I_MIXER_DE33, + .scaler_mask =3D 0xf, + .scanline_yuv =3D 4096, + }, .de_type =3D SUN8I_MIXER_DE33, .mod_rate =3D 600000000, - .scaler_mask =3D 0xf, - .scanline_yuv =3D 4096, .ui_num =3D 3, .vi_num =3D 1, .map =3D {0, 6, 7, 8}, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/su= n8i_mixer.h index 40b800022237..8629e21f9cf6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -164,34 +164,44 @@ enum sun8i_mixer_type { }; =20 /** - * struct sun8i_mixer_cfg - mixer HW configuration - * @vi_num: number of VI channels - * @ui_num: number of UI channels + * struct sun8i_layer_cfg - layer configuration * @scaler_mask: bitmask which tells which channel supports scaling * First, scaler supports for VI channels is defined and after that, scaler * support for UI channels. For example, if mixer has 2 VI channels without * scaler and 2 UI channels with scaler, bitmask would be 0xC. * @ccsc: select set of CCSC base addresses from the enumeration above. - * @mod_rate: module clock rate that needs to be set in order to have - * a functional block. * @de_type: sun8i_mixer_type enum representing the display engine generat= ion. * @scaline_yuv: size of a scanline for VI scaler for YUV formats. * @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability * Most DE2 cores has FCC. If number of VI planes is one, enable this. * @vi_scaler_num: Number of VI scalers. Used on DE2 and DE3. - * @map: channel map for DE variants processing YUV separately (DE33) */ -struct sun8i_mixer_cfg { - int vi_num; - int ui_num; +struct sun8i_layer_cfg { int scaler_mask; int ccsc; - unsigned long mod_rate; unsigned int de_type; unsigned int scanline_yuv; unsigned int de2_fcc_alpha : 1; unsigned int vi_scaler_num; - unsigned int map[6]; +}; + +/** + * struct sun8i_mixer_cfg - mixer HW configuration + * @lay_cfg: layer configuration + * @vi_num: number of VI channels + * @ui_num: number of UI channels + * @mod_rate: module clock rate that needs to be set in order to have + * a functional block. + * @map: channel map for DE variants processing YUV separately (DE33) + */ + +struct sun8i_mixer_cfg { + struct sun8i_layer_cfg lay_cfg; + int vi_num; + int ui_num; + unsigned int de_type; + unsigned long mod_rate; + unsigned int map[6]; }; =20 struct sun8i_mixer { diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i= /sun8i_ui_layer.c index e65dc313c87d..f71f5a8d0427 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -190,7 +190,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane= *plane, min_scale =3D DRM_PLANE_NO_SCALING; max_scale =3D DRM_PLANE_NO_SCALING; =20 - if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { + if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) { min_scale =3D SUN8I_UI_SCALER_SCALE_MIN; max_scale =3D SUN8I_UI_SCALER_SCALE_MAX; } diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4= i/sun8i_ui_scaler.c index 0ba1482688d7..4d06c366de7f 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c @@ -91,7 +91,7 @@ static const u32 lan2coefftab16[240] =3D { =20 static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel) { - int offset =3D mixer->cfg->vi_scaler_num; + int offset =3D mixer->cfg->lay_cfg.vi_scaler_num; =20 if (mixer->cfg->de_type =3D=3D SUN8I_MIXER_DE3) return DE3_VI_SCALER_UNIT_BASE + diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.c index 8eb3f167e664..0286e7322612 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -53,7 +53,7 @@ static void sun8i_vi_layer_update_attributes(struct sun8i= _layer *layer, regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val); =20 - if (mixer->cfg->de2_fcc_alpha) { + if (mixer->cfg->lay_cfg.de2_fcc_alpha) { regmap_write(layer->regs, SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG, SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8)); @@ -152,7 +152,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_la= yer *layer, } =20 /* it seems that every RGB scaler has buffer for 2048 pixels */ - scanline =3D subsampled ? mixer->cfg->scanline_yuv : 2048; + scanline =3D subsampled ? mixer->cfg->lay_cfg.scanline_yuv : 2048; =20 if (src_w > scanline) { DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n"); @@ -278,7 +278,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane= *plane, min_scale =3D DRM_PLANE_NO_SCALING; max_scale =3D DRM_PLANE_NO_SCALING; =20 - if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { + if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) { min_scale =3D SUN8I_VI_SCALER_SCALE_MIN; max_scale =3D SUN8I_VI_SCALER_SCALE_MAX; } @@ -452,7 +452,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_= device *drm, return ERR_PTR(ret); } =20 - if (mixer->cfg->de2_fcc_alpha || mixer->cfg->de_type >=3D SUN8I_MIXER_DE3= ) { + if (mixer->cfg->lay_cfg.de2_fcc_alpha || mixer->cfg->de_type >=3D SUN8I_M= IXER_DE3) { ret =3D drm_plane_create_alpha_property(&layer->plane); if (ret) { dev_err(drm->dev, "Couldn't add alpha property\n"); --=20 2.51.0