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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d67d8283sm760176466b.38.2025.10.12.12.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Oct 2025 12:24:03 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 20/30] drm/sun4i: layers: Make regmap for layers configurable Date: Sun, 12 Oct 2025 21:23:20 +0200 Message-ID: <20251012192330.6903-21-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251012192330.6903-1-jernej.skrabec@gmail.com> References: <20251012192330.6903-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Till DE33, there were no reason to decouple registers from mixer. However, with future new plane driver, this will be necessary. Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 7 ++++-- drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 12 ++++++---- drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 1 + drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 16 ++++++------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 ++++++++++-------- drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 1 + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 31 ++++++++++++------------- 8 files changed, 50 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index 18dd998364ae..d2b7fc552a76 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -331,7 +331,9 @@ static struct drm_plane **sun8i_layers_init(struct drm_= device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - layer =3D sun8i_vi_layer_init_one(drm, mixer, type, i, plane_cnt); + layer =3D sun8i_vi_layer_init_one(drm, mixer, type, + mixer->engine.regs, i, + plane_cnt); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize overlay plane\n"); @@ -350,7 +352,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_= device *drm, else type =3D DRM_PLANE_TYPE_OVERLAY; =20 - layer =3D sun8i_ui_layer_init_one(drm, mixer, type, index, + layer =3D sun8i_ui_layer_init_one(drm, mixer, type, + mixer->engine.regs, index, plane_cnt); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize %s plane\n", diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/su= n8i_mixer.h index b5badfa2c997..2e3689008b50 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -214,6 +214,7 @@ struct sun8i_layer { int type; int channel; int overlay; + struct regmap *regs; }; =20 static inline struct sun8i_layer * diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i= /sun8i_ui_layer.c index 5167c9d7b9c0..dd6cb09c2c01 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -53,7 +53,7 @@ static void sun8i_ui_layer_update_attributes(struct sun8i= _layer *layer, val |=3D hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; val |=3D SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), val); } =20 @@ -87,10 +87,10 @@ static void sun8i_ui_layer_update_coord(struct sun8i_la= yer *layer, DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", state->src.x1 >> 16, state->src.y1 >> 16); DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, layer->overlay), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base), insize); =20 @@ -149,13 +149,13 @@ static void sun8i_ui_layer_update_buffer(struct sun8i= _layer *layer, =20 /* Set the line width */ DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, layer->overlay), fb->pitches[0]); =20 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr); =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, layer->overlay), lower_32_bits(dma_addr)); } @@ -264,6 +264,7 @@ static const uint64_t sun8i_layer_modifiers[] =3D { struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt) { @@ -278,6 +279,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_= device *drm, layer->type =3D SUN8I_LAYER_TYPE_UI; layer->channel =3D index; layer->overlay =3D 0; + layer->regs =3D regs; =20 /* possible crtcs are set later */ ret =3D drm_universal_plane_init(drm, &layer->plane, 0, diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i= /sun8i_ui_layer.h index 0613b34d36e0..e0b2cfa02749 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h @@ -52,6 +52,7 @@ struct sun8i_layer; struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt); #endif /* _SUN8I_UI_LAYER_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4= i/sun8i_ui_scaler.c index fcd72c4fd49a..2fc54dc20307 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c @@ -143,7 +143,7 @@ void sun8i_ui_scaler_enable(struct sun8i_layer *layer, = bool enable) else val =3D 0; =20 - regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val); + regmap_write(layer->regs, SUN8I_SCALER_GSU_CTRL(base), val); } =20 void sun8i_ui_scaler_setup(struct sun8i_layer *layer, @@ -168,22 +168,22 @@ void sun8i_ui_scaler_setup(struct sun8i_layer *layer, insize =3D SUN8I_UI_SCALER_SIZE(src_w, src_h); outsize =3D SUN8I_UI_SCALER_SIZE(dst_w, dst_h); =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_OUTSIZE(base), outsize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_INSIZE(base), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HSTEP(base), hscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_VSTEP(base), vscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HPHASE(base), hphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_VPHASE(base), vphase); offset =3D sun8i_ui_scaler_coef_index(hscale) * SUN8I_UI_SCALER_COEFF_COUNT; for (i =3D 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++) - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HCOEFF(base, i), lan2coefftab16[offset + i]); } diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.c index ce71625fa06f..2290c983e177 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -49,12 +49,12 @@ static void sun8i_vi_layer_update_attributes(struct sun= 8i_layer *layer, SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL : SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED; } else if (mixer->cfg->vi_num =3D=3D 1) { - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG, SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8)); } =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val); } =20 @@ -112,10 +112,10 @@ static void sun8i_vi_layer_update_coord(struct sun8i_= layer *layer, (state->src.x1 >> 16) & ~(format->hsub - 1), (state->src.y1 >> 16) & ~(format->vsub - 1)); DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, layer->overlay), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base), insize); =20 @@ -170,19 +170,19 @@ static void sun8i_vi_layer_update_coord(struct sun8i_= layer *layer, sun8i_vi_scaler_enable(layer, false); } =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(hn) | SUN8I_MIXER_CHAN_VI_DS_M(hm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(hn) | SUN8I_MIXER_CHAN_VI_DS_M(hm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(vn) | SUN8I_MIXER_CHAN_VI_DS_M(vm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(vn) | SUN8I_MIXER_CHAN_VI_DS_M(vm)); @@ -231,7 +231,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_l= ayer *layer, /* Set the line width */ DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n", i + 1, fb->pitches[i]); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base, layer->overlay, i), fb->pitches[i]); @@ -239,7 +239,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_l= ayer *layer, DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n", i + 1, &dma_addr); =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base, layer->overlay, i), lower_32_bits(dma_addr)); @@ -410,6 +410,7 @@ static const uint64_t sun8i_layer_modifiers[] =3D { struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt) { @@ -427,6 +428,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_= device *drm, layer->type =3D SUN8I_LAYER_TYPE_VI; layer->channel =3D index; layer->overlay =3D 0; + layer->regs =3D regs; =20 if (mixer->cfg->de_type >=3D SUN8I_MIXER_DE3) { formats =3D sun8i_vi_layer_de3_formats; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.h index a568e1db1e19..70766d752fa6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h @@ -57,6 +57,7 @@ struct sun8i_layer; struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt); #endif /* _SUN8I_VI_LAYER_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4= i/sun8i_vi_scaler.c index a76677a1649f..0e308feb492a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c @@ -911,10 +911,9 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *m= ap, u32 base, =20 void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable) { - struct sun8i_mixer *mixer =3D layer->mixer; u32 val, base; =20 - base =3D sun8i_vi_scaler_base(mixer, layer->channel); + base =3D sun8i_vi_scaler_base(layer->mixer, layer->channel); =20 if (enable) val =3D SUN8I_SCALER_VSU_CTRL_EN | @@ -922,7 +921,7 @@ void sun8i_vi_scaler_enable(struct sun8i_layer *layer, = bool enable) else val =3D 0; =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CTRL(base), val); } =20 @@ -968,36 +967,36 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer, else val =3D SUN50I_SCALER_VSU_SCALE_MODE_NORMAL; =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN50I_SCALER_VSU_SCALE_MODE(base), val); } =20 - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_OUTSIZE(base), outsize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YINSIZE(base), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YHSTEP(base), hscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YVSTEP(base), vscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YHPHASE(base), hphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YVPHASE(base), vphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CINSIZE(base), SUN8I_VI_SCALER_SIZE(src_w / format->hsub, src_h / format->vsub)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CHSTEP(base), hscale / format->hsub); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CVSTEP(base), vscale / format->vsub); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CHPHASE(base), chphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CVPHASE(base), cvphase); - sun8i_vi_scaler_set_coeff(mixer->engine.regs, base, + sun8i_vi_scaler_set_coeff(layer->regs, base, hscale, vscale, format); } --=20 2.51.0