From nobody Wed Dec 17 10:56:01 2025 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FFEB27FB37 for ; Fri, 10 Oct 2025 23:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139415; cv=none; b=D/K9pDxW0HUtdkD9XJTCmkLKL08JyuMgM/2aNNfzHJ4Pm553D3TFPTw77yDqZe7LZ0Hj0jwI4BydbuDV+vBY+R/5Xmtx6rBvaqJZxppTTOzq34sh300B+9nM8AsEnrJHLLZiiK+GcZP8V38hyl8TCTcZV6KXtpfGiI2Lucbzl7s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139415; c=relaxed/simple; bh=yn549GC5MTVOmDeuKYorX8vzwQVzn0ayeG7Hx9nghZg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iEFp5jr83cbEhvozc84GjqOdS0S66wPyMxG0u39K4bqxTrFNkVO+MqiKKb8+My/mpKK3G2Cc54zelq6IePZ09MaLtRhbNwpIhNC6vsdojKJMpE3r8Mmq0pcAJVJGGM7T9AUxMZvNoew1vJ114uur0xg4d0lXetmLNDQTkF8J8es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.81.247]) by APP-05 (Coremail) with SMTP id zQCowADHaxVUmOloXC2IDQ--.41211S3; Sat, 11 Oct 2025 07:35:48 +0800 (CST) From: Vivian Wang Date: Sat, 11 Oct 2025 07:35:43 +0800 Subject: [PATCH v3 1/5] riscv: pgtable: Use __riscv_has_extension_unlikely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251011-riscv-altn-helper-wip-v3-1-d40ddaa1985a@iscas.ac.cn> References: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> In-Reply-To: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: zQCowADHaxVUmOloXC2IDQ--.41211S3 X-Coremail-Antispam: 1UD129KBjvJXoWxJFWUKFW8uF4rXr1fJF45trb_yoW5Cw1Upr Z3CasxWrWrCw1xurZ2yr4DCr45Z39ag3W3Kr1S93WrAr4akw42vrnxJ3Wayry8Ja97X348 KF4akr45W3W3Ar7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIx AIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2 KfnxnUUI43ZEXa7VUjrHUDUUUUU== X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use __riscv_has_extension_unlikely() to check for RISCV_ISA_EXT_SVVPTC, replacing the use of asm goto with ALTERNATIVE. The "unlikely" variant is used to match the behavior of the original implementation using ALTERNATIVE("nop", "j %l[svvptc]", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/pgtable.h | 15 +++++++-------- arch/riscv/mm/pgtable.c | 22 ++++++++++------------ 2 files changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 29e994a9afb67c638173d4a2475fdfbd91bee967..02f37322eb83a113b411e95e153= fecc5c20319ad 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -496,8 +496,13 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, struct vm_area_struct *vma, unsigned long address, pte_t *ptep, unsigned int nr) { - asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) - : : : : svvptc); + /* + * Svvptc guarantees that the new valid pte will be visible within + * a bounded timeframe, so when the uarch does not cache invalid + * entries, we don't have to do anything. + */ + if (__riscv_has_extension_unlikely(0, RISCV_ISA_EXT_SVVPTC)) + return; =20 /* * The kernel assumes that TLBs don't cache invalid entries, but @@ -509,12 +514,6 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, while (nr--) local_flush_tlb_page(address + nr * PAGE_SIZE); =20 -svvptc:; - /* - * Svvptc guarantees that the new valid pte will be visible within - * a bounded timeframe, so when the uarch does not cache invalid - * entries, we don't have to do anything. - */ } #define update_mmu_cache(vma, addr, ptep) \ update_mmu_cache_range(NULL, vma, addr, ptep, 1) diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c index 8b6c0a112a8db4e91de54c3bd3bd527a605a6197..289ca6fa6b4de80d42287d28e26= 6a0a8d3848cff 100644 --- a/arch/riscv/mm/pgtable.c +++ b/arch/riscv/mm/pgtable.c @@ -9,8 +9,16 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, pte_t *ptep, pte_t entry, int dirty) { - asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) - : : : : svvptc); + if (__riscv_has_extension_unlikely(0, RISCV_ISA_EXT_SVVPTC)) { + if (!pte_same(ptep_get(ptep), entry)) { + __set_pte_at(vma->vm_mm, ptep, entry); + /* Here only not svadu is impacted */ + flush_tlb_page(vma, address); + return true; + } + + return false; + } =20 if (!pte_same(ptep_get(ptep), entry)) __set_pte_at(vma->vm_mm, ptep, entry); @@ -19,16 +27,6 @@ int ptep_set_access_flags(struct vm_area_struct *vma, * the case that the PTE changed and the spurious fault case. */ return true; - -svvptc: - if (!pte_same(ptep_get(ptep), entry)) { - __set_pte_at(vma->vm_mm, ptep, entry); - /* Here only not svadu is impacted */ - flush_tlb_page(vma, address); - return true; - } - - return false; } =20 int ptep_test_and_clear_young(struct vm_area_struct *vma, --=20 2.50.1 From nobody Wed Dec 17 10:56:01 2025 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB51927FB2E for ; Fri, 10 Oct 2025 23:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139415; cv=none; b=Cf8aQWkjx6/rvdhCjzugdkite3U09zgYL71jPS9qkS7h2GO5xdOUxw1y9EhkBqodwVG52ObtcaX5TtfmF3+IxtfoxNRQMld9sv+gLtcMeqj9XbYf8Xbl0jUGsMTyo7WrjyULqzO05L+V48/hdHxxdZeNppTXZebXjoSAhOBuauc= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251011-riscv-altn-helper-wip-v3-2-d40ddaa1985a@iscas.ac.cn> References: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> In-Reply-To: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: zQCowADHaxVUmOloXC2IDQ--.41211S4 X-Coremail-Antispam: 1UD129KBjvJXoW3WFy7CF17XF4DXw47JFW5Wrg_yoW7XF17pr s3trWfKrykAa4YkryqyrZ5urn8Xw4kGwn8KrsxGry8JF90y3y3Kr95tF1fAry5XFyxta4S vayfuw13uF1Yya7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIx AIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2 KfnxnUUI43ZEXa7VUbH5lUUUUUU== X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use __riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[no_zbb]", "nop", ...). While we're at it, also remove bogus comment about Zbb being likely available. We have to choose between "likely" and "unlikely" due to limitations of the asm goto feature, but that does not mean we should put a bad comment on why we pick "likely" over "unlikely". Signed-off-by: Vivian Wang --- arch/riscv/include/asm/checksum.h | 13 +++------- arch/riscv/lib/csum.c | 53 +++++++++--------------------------= ---- 2 files changed, 16 insertions(+), 50 deletions(-) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h index da378856f1d590e22271b90e803c7e55e8dd22e3..70eb50173fb6ab636f9e1534ce2= ba58de5ee5c54 100644 --- a/arch/riscv/include/asm/checksum.h +++ b/arch/riscv/include/asm/checksum.h @@ -49,16 +49,11 @@ static inline __sum16 ip_fast_csum(const void *iph, uns= igned int ihl) * ZBB only saves three instructions on 32-bit and five on 64-bit so not * worth checking if supported without Alternatives. */ - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - if (IS_ENABLED(CONFIG_32BIT)) { asm(".option push \n\ .option arch,+zbb \n\ @@ -81,7 +76,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsig= ned int ihl) } return (__force __sum16)(csum >> 16); } -no_zbb: + #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index 9408f50ca59a8901f7cfbcf3297d1492172c6ea2..420e9eb93e8531bb988823e46f2= 3b0bbb7ca0afb 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -40,20 +40,11 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, uproto =3D (__force unsigned int)htonl(proto); sum +=3D uproto; =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); asm(".option push \n\ .option arch,+zbb \n\ rori %[fold_temp], %[sum], 32 \n\ @@ -66,7 +57,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, : [sum] "+r" (sum), [fold_temp] "=3D&r" (fold_temp)); return (__force __sum16)(sum >> 16); } -no_zbb: + sum +=3D ror64(sum, 32); sum >>=3D 32; return csum_fold((__force __wsum)sum); @@ -152,21 +143,11 @@ do_csum_with_alignment(const unsigned char *buff, int= len) csum =3D do_csum_common(ptr, end, data); =20 #ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - #ifdef CONFIG_32BIT asm_goto_output(".option push \n\ .option arch,+zbb \n\ @@ -204,7 +185,7 @@ do_csum_with_alignment(const unsigned char *buff, int l= en) end: return csum >> 16; } -no_zbb: + #endif /* CC_HAS_ASM_GOTO_TIED_OUTPUT */ #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); @@ -234,21 +215,11 @@ do_csum_no_alignment(const unsigned char *buff, int l= en) end =3D (const unsigned long *)(buff + len); csum =3D do_csum_common(ptr, end, data); =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - #ifdef CONFIG_32BIT asm (".option push \n\ .option arch,+zbb \n\ @@ -274,7 +245,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) #endif /* !CONFIG_32BIT */ return csum >> 16; } -no_zbb: + #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; --=20 2.50.1 From nobody Wed Dec 17 10:56:01 2025 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D443D27FD49 for ; Fri, 10 Oct 2025 23:36:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139414; cv=none; b=p3Evk+sLceqOTkq9qWVn/d5JbR9i6it00TsMVbTb0KxCjsdkwyxN56YxuQngQHria6BwJhpXVbaiC0fiWcDAKrV5kdVbn76UOSZjkJU0IZnZ8uBKFhFnKJBfpSZLHPFig0AHf0eSBIvZ7S8xan5knky7ABqVa/e5AQu7rvqrDb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139414; c=relaxed/simple; bh=FFka5n39TNHtjOEHhQvzXdQxF9OR9QCVkKcO9IfY9QI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RS9aYOMhzCTmJ3jePdSxI1hMzXrO1Xa9susmyQ6n9a3lMVqgakPdhNbqID4OMtbZbcoKTgF8SEQXVn+6tAXYEZXy7WiJqbtzDBEavEcrRb2gppvvrrDt8BMOhvg8A5abyMLcYQ4Ds9EAoWSa0cMPrUX61hDrY/vBKWDwTjN3LQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.81.247]) by APP-05 (Coremail) with SMTP id zQCowADHaxVUmOloXC2IDQ--.41211S5; Sat, 11 Oct 2025 07:35:48 +0800 (CST) From: Vivian Wang Date: Sat, 11 Oct 2025 07:35:45 +0800 Subject: [PATCH v3 3/5] riscv: hweight: Use __riscv_has_extension_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251011-riscv-altn-helper-wip-v3-3-d40ddaa1985a@iscas.ac.cn> References: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> In-Reply-To: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: zQCowADHaxVUmOloXC2IDQ--.41211S5 X-Coremail-Antispam: 1UD129KBjvJXoW7Aw4kWFy8WrWDtF43Zw48Xrb_yoW8KF4kpF 4Iy3s3GFWkJa18uF90yr1kZa1rZan3G347GrW3u3yxXFyjyw4Ykrn8KFn8Cr98tFyvv3WS qFWfA343u3W2qaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4U JwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE bVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67 AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI 42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCw CI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnI WIevJa73UjIFyTuYvjfUO_MaUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use __riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[legacy]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/arch_hweight.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm= /arch_hweight.h index 0e7cdbbec8efd3c293da2fa96a8c6d0a93faf56f..021bc671de299d604a33301e68c= 10cb1c28ad2c1 100644 --- a/arch/riscv/include/asm/arch_hweight.h +++ b/arch/riscv/include/asm/arch_hweight.h @@ -19,10 +19,10 @@ =20 static __always_inline unsigned int __arch_hweight32(unsigned int w) { -#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB))) + return __sw_hweight32(w); =20 asm (".option push\n" ".option arch,+zbb\n" @@ -31,10 +31,6 @@ static __always_inline unsigned int __arch_hweight32(uns= igned int w) : "=3Dr" (w) : "r" (w) :); =20 return w; - -legacy: -#endif - return __sw_hweight32(w); } =20 static inline unsigned int __arch_hweight16(unsigned int w) @@ -50,10 +46,10 @@ static inline unsigned int __arch_hweight8(unsigned int= w) #if BITS_PER_LONG =3D=3D 64 static __always_inline unsigned long __arch_hweight64(__u64 w) { -#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + __riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB))) + return __sw_hweight64(w); =20 asm (".option push\n" ".option arch,+zbb\n" @@ -62,10 +58,6 @@ static __always_inline unsigned long __arch_hweight64(__= u64 w) : "=3Dr" (w) : "r" (w) :); =20 return w; - -legacy: -#endif - return __sw_hweight64(w); } #else /* BITS_PER_LONG =3D=3D 64 */ static inline unsigned long __arch_hweight64(__u64 w) --=20 2.50.1 From nobody Wed Dec 17 10:56:01 2025 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 902A126D4FB for ; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.81.247]) by APP-05 (Coremail) with SMTP id zQCowADHaxVUmOloXC2IDQ--.41211S6; Sat, 11 Oct 2025 07:35:49 +0800 (CST) From: Vivian Wang Date: Sat, 11 Oct 2025 07:35:46 +0800 Subject: [PATCH v3 4/5] riscv: bitops: Use __riscv_has_extension_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251011-riscv-altn-helper-wip-v3-4-d40ddaa1985a@iscas.ac.cn> References: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> In-Reply-To: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: zQCowADHaxVUmOloXC2IDQ--.41211S6 X-Coremail-Antispam: 1UD129KBjvJXoWxGrW8Kw18Kw4kWr15tr18Krg_yoW5Crykpr 95K347JFWDta45uFZFyryfXr4ruw47G393GrWS93y8AFWUA39a9r90k3WFkr15AFWvga47 Zr4UJ3s3W3W5Xw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE 7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI 8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWU CwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIY CTnIWIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use __riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[legacy]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/bitops.h | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitop= s.h index 77880677b06e03875721f33515a6d2ac9166c373..d566747a341bb2e04a63eb54556= 56fd73585bc55 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -47,9 +47,8 @@ =20 static __always_inline __attribute_const__ unsigned long variable__ffs(uns= igned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!__riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) + return generic___ffs(word); =20 asm volatile (".option push\n" ".option arch,+zbb\n" @@ -58,9 +57,6 @@ static __always_inline __attribute_const__ unsigned long = variable__ffs(unsigned : "=3Dr" (word) : "r" (word) :); =20 return word; - -legacy: - return generic___ffs(word); } =20 /** @@ -76,9 +72,8 @@ static __always_inline __attribute_const__ unsigned long = variable__ffs(unsigned =20 static __always_inline __attribute_const__ unsigned long variable__fls(uns= igned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!__riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) + return generic___fls(word); =20 asm volatile (".option push\n" ".option arch,+zbb\n" @@ -87,9 +82,6 @@ static __always_inline __attribute_const__ unsigned long = variable__fls(unsigned : "=3Dr" (word) : "r" (word) :); =20 return BITS_PER_LONG - 1 - word; - -legacy: - return generic___fls(word); } =20 /** @@ -105,9 +97,8 @@ static __always_inline __attribute_const__ unsigned long= variable__fls(unsigned =20 static __always_inline __attribute_const__ int variable_ffs(int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!__riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) + return generic_ffs(x); =20 if (!x) return 0; @@ -119,9 +110,6 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) : "=3Dr" (x) : "r" (x) :); =20 return x + 1; - -legacy: - return generic_ffs(x); } =20 /** @@ -137,9 +125,8 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) =20 static __always_inline int variable_fls(unsigned int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (!__riscv_has_extension_likely(0, RISCV_ISA_EXT_ZBB)) + return generic_fls(x); =20 if (!x) return 0; @@ -151,9 +138,6 @@ static __always_inline int variable_fls(unsigned int x) : "=3Dr" (x) : "r" (x) :); =20 return 32 - x; - -legacy: - return generic_fls(x); } =20 /** --=20 2.50.1 From nobody Wed Dec 17 10:56:01 2025 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E0627FB2D for ; Fri, 10 Oct 2025 23:36:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760139414; cv=none; b=Q0riOrmtExxxx95wNBDCCJ7r519YCk6P44UNPku36HXaOZ2eEuSE75Tb8/G0yFjAWvZxH8YyBChC0Tcsh8cL5kpxf+b7pIMMBSWJ15I+HZpKO0SD0HQQ2pfEPeTHg4rQeGm8Yokz3TuleXpPrXCnB247SRHdgLQXTjPrKV0Sk+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251011-riscv-altn-helper-wip-v3-5-d40ddaa1985a@iscas.ac.cn> References: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> In-Reply-To: <20251011-riscv-altn-helper-wip-v3-0-d40ddaa1985a@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes , Paul Walmsley Cc: Charlie Jenkins , Xiao Wang , =?utf-8?q?Christoph_M=C3=BCllner?= , Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: zQCowADHaxVUmOloXC2IDQ--.41211S7 X-Coremail-Antispam: 1UD129KBjvJXoW7CF48uw17uw4rKF1fKrW5GFg_yoW8JFyxpr ZxCr1jkFyDCw4xZa9Yyr9xXw4rX39xK3W3CFWj9a48JFWUAryfArn0v3W5ur1UJFZ2q34Y vFWrC3s3Z3W7trJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE 7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI 8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8 JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJV WUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIY CTnIWIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use __riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZAWRS, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[no_zawrs]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/cmpxchg.h | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 122e1485d39a0ad44ec4357cb23148dc6e58dc6b..6fca79f5c3475cc03745e481f96= 4d2899373235b 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -373,9 +373,10 @@ static __always_inline void __cmpwait(volatile void *p= tr, u32 *__ptr32b; ulong __s, __val, __mask; =20 - asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop", - 0, RISCV_ISA_EXT_ZAWRS, 1) - : : : : no_zawrs); + if (!__riscv_has_extension_likely(0, RISCV_ISA_EXT_ZAWRS)) { + ALT_RISCV_PAUSE(); + return; + } =20 switch (size) { case 1: @@ -437,11 +438,6 @@ static __always_inline void __cmpwait(volatile void *p= tr, default: BUILD_BUG(); } - - return; - -no_zawrs: - ALT_RISCV_PAUSE(); } =20 #define __cmpwait_relaxed(ptr, val) \ --=20 2.50.1