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AJvYcCUt6HhSh3O+ut4xgT/5hJaxT9k33m7t/cTVfMUHXrocNDMLH1sY1SYF5G+eBP27jPlPthnpQhCWY7vR7oM=@vger.kernel.org X-Gm-Message-State: AOJu0YxD3mHzwhUYwn6Sw5eywTt3Z2aOmtx9sqcmdunlzMeWarXrTHMx 3/M02EB2nHRdsgtubQz2oq/lWvTnbx/BjBjTGH0recpuuLXUOnBmM671y9QD0zHTnSLD5bzMxrj zGeXYhg== X-Google-Smtp-Source: AGHT+IG2O2/hmz4EGHxbz6LI/FnWz/lYeOwpP5uEupOv3mruD2AaSSt/AAWUjN2TixtwciX5BwSqJ0FHSFw= X-Received: from pjff6.prod.google.com ([2002:a17:90b:5626:b0:330:6c04:207]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4a83:b0:32e:b87e:a961 with SMTP id 98e67ed59e1d1-33b511173bfmr19125944a91.5.1760127389914; Fri, 10 Oct 2025 13:16:29 -0700 (PDT) Date: Fri, 10 Oct 2025 20:16:06 +0000 In-Reply-To: <20251010201607.1190967-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251010201607.1190967-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.740.g6adb054d12-goog Message-ID: <20251010201607.1190967-4-royluo@google.com> Subject: [PATCH v3 3/4] dt-bindings: phy: google: Add Google Tensor G5 USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation. The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Signed-off-by: Roy Luo --- .../bindings/phy/google,gs5-usb-phy.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-ph= y.yaml diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml = b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml new file mode 100644 index 000000000000..a40de31ac768 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) USB PHY + +maintainers: + - Roy Luo + +description: | + Describes the USB PHY interfaces integrated with the DWC3 USB controller= on + Google Tensor SoCs, starting with the G5 generation. + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PH= Y IP + and USB 3.2/DisplayPort combo PHY IP. + The hardware can support three PHY interfaces, which are selected using = the + first phandle argument in the PHY specifier:: + 0 - USB high-speed. + 1 - USB super-speed. + 2 - DisplayPort + +properties: + compatible: + const: google,gs5-usb-phy + + reg: + items: + - description: USB2 PHY configuration registers. + - description: DisplayPort top-level registers. + - description: USB top-level configuration registers. + + reg-names: + items: + - const: u2phy_cfg + - const: dp_top + - const: usb_top_cfg + + "#phy-cells": + const: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - resets + - power-domains + - orientation-switch + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb_phy: usb_phy@c410000 { + compatible =3D "google,gs5-usb-phy"; + reg =3D <0 0x0c450014 0 0xc>, + <0 0x0c637000 0 0xa0>, + <0 0x0c45002c 0 0x4>; + reg-names =3D "u2phy_cfg", "dp_top", "usb_top_cfg"; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_reset_clk>; + resets =3D <&hsion_resets_usb2_phy>; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + }; + }; +... --=20 2.51.0.740.g6adb054d12-goog