From nobody Fri Dec 19 14:01:15 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CC8D2F8BEE for ; Fri, 10 Oct 2025 15:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760111260; cv=none; b=c7LopQstFoj22brbKHmCRBf9la1Xw5PldN8bX+3qu3l1Rs2oGzYcnf+CDuXwRdSv21VkWEhkFlXiqmuEDa0Zpe2CWSYdV/r+ObDa+dAQB4uXuHgfGNIu4iKprrqQnvunuK8GS+h992BDV85OeNp1ycugu8zIxGpOOPlRYXFEnws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760111260; c=relaxed/simple; bh=C71Q+gqxu3FdMOCm94VISW42L1WJ3pD4CusQBfFzOYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t8BVJX5uOuv00uFQ7jIgbKAYhpWjio5/7Dvi+JpfM0MEwKR4kZn7P2IbTl+nenX+W16SyxksuHcFOyqHk0KyGu8zjheQRbsRQHEwLOYWEqxE/G5I27AKLDdK+zWDonHh5dKsfEijNTS6H8ekUT0ldoaRF60f12amwZ28w9BdiSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=QwaLgr/h; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="QwaLgr/h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760111258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tZSxQNDyqaqLbPz4fQtAMe+wkuer6c/+cc0bKB75WPM=; b=QwaLgr/hvQX1ABeWK0m/ZRAQXS09j5HK8tRmdjBQGJ3NftTIPe7Zd78QCy4h2b8v6m7PxE GRNZg/Ys1VKlNk5BlNsRgxarEbB9wqjFCeSB6uTYBbr1QrWNd5JXQgqnDpBqtRoWpudxoo 6wNuQZWwk2pS55Ybq0rXIH/aMIhZqdw= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-384-gHsLeaZYN2q0fujOe0R-ug-1; Fri, 10 Oct 2025 11:47:35 -0400 X-MC-Unique: gHsLeaZYN2q0fujOe0R-ug-1 X-Mimecast-MFC-AGG-ID: gHsLeaZYN2q0fujOe0R-ug_1760111251 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id F0A791956096; Fri, 10 Oct 2025 15:47:30 +0000 (UTC) Received: from vschneid-thinkpadt14sgen2i.remote.csb (unknown [10.45.224.29]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id EDAAF180035E; Fri, 10 Oct 2025 15:47:15 +0000 (UTC) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, rcu@vger.kernel.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-trace-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Arnaldo Carvalho de Melo , Josh Poimboeuf , Paolo Bonzini , Arnd Bergmann , Frederic Weisbecker , "Paul E. McKenney" , Jason Baron , Steven Rostedt , Ard Biesheuvel , Sami Tolvanen , "David S. Miller" , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Boqun Feng , Uladzislau Rezki , Mathieu Desnoyers , Mel Gorman , Andrew Morton , Masahiro Yamada , Han Shen , Rik van Riel , Jann Horn , Dan Carpenter , Oleg Nesterov , Juri Lelli , Clark Williams , Yair Podemsky , Marcelo Tosatti , Daniel Wagner , Petr Tesarik Subject: [RFC PATCH v6 26/29] x86/mm/pti: Introduce a kernel/user CR3 software signal Date: Fri, 10 Oct 2025 17:38:36 +0200 Message-ID: <20251010153839.151763-27-vschneid@redhat.com> In-Reply-To: <20251010153839.151763-1-vschneid@redhat.com> References: <20251010153839.151763-1-vschneid@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Later commits will rely on this information to defer kernel TLB flush IPIs. Update it when switching to and from the kernel CR3. This will only be really useful for NOHZ_FULL CPUs, but it should be cheaper to unconditionally update a never-used per-CPU variable living in its own cacheline than to check a shared cpumask such as housekeeping_cpumask(HK_TYPE_KERNEL_NOISE) at every entry. Note that the COALESCE_TLBI config option is introduced in a later commit, when the whole feature is implemented. Signed-off-by: Valentin Schneider --- Per the cover letter, I really hate this, but couldn't come up with anything better. --- arch/x86/entry/calling.h | 16 ++++++++++++++++ arch/x86/entry/syscall_64.c | 4 ++++ arch/x86/include/asm/tlbflush.h | 3 +++ 3 files changed, 23 insertions(+) diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h index 94519688b0071..813451b1ddecc 100644 --- a/arch/x86/entry/calling.h +++ b/arch/x86/entry/calling.h @@ -171,11 +171,24 @@ For 32-bit we have the following conventions - kernel= is built with andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg .endm +.macro COALESCE_TLBI +#ifdef CONFIG_COALESCE_TLBI + movl $1, PER_CPU_VAR(kernel_cr3_loaded) +#endif // CONFIG_COALESCE_TLBI +.endm + +.macro NOTE_SWITCH_TO_USER_CR3 +#ifdef CONFIG_COALESCE_TLBI + movl $0, PER_CPU_VAR(kernel_cr3_loaded) +#endif // CONFIG_COALESCE_TLBI +.endm + .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI mov %cr3, \scratch_reg ADJUST_KERNEL_CR3 \scratch_reg mov \scratch_reg, %cr3 + COALESCE_TLBI .Lend_\@: .endm @@ -183,6 +196,7 @@ For 32-bit we have the following conventions - kernel i= s built with PER_CPU_VAR(cpu_tlbstate + TLB_STATE_user_pcid_flush_mask) .macro SWITCH_TO_USER_CR3 scratch_reg:req scratch_reg2:req + NOTE_SWITCH_TO_USER_CR3 mov %cr3, \scratch_reg ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID @@ -242,6 +256,7 @@ For 32-bit we have the following conventions - kernel i= s built with ADJUST_KERNEL_CR3 \scratch_reg movq \scratch_reg, %cr3 + COALESCE_TLBI .Ldone_\@: .endm @@ -258,6 +273,7 @@ For 32-bit we have the following conventions - kernel i= s built with bt $PTI_USER_PGTABLE_BIT, \save_reg jnc .Lend_\@ + NOTE_SWITCH_TO_USER_CR3 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID /* diff --git a/arch/x86/entry/syscall_64.c b/arch/x86/entry/syscall_64.c index b6e68ea98b839..2589d232e0ba1 100644 --- a/arch/x86/entry/syscall_64.c +++ b/arch/x86/entry/syscall_64.c @@ -83,6 +83,10 @@ static __always_inline bool do_syscall_x32(struct pt_reg= s *regs, int nr) return false; } +#ifdef CONFIG_COALESCE_TLBI +DEFINE_PER_CPU(bool, kernel_cr3_loaded) =3D true; +#endif + /* Returns true to return using SYSRET, or false to use IRET */ __visible noinstr bool do_syscall_64(struct pt_regs *regs, int nr) { diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 00daedfefc1b0..e39ae95b85072 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -17,6 +17,9 @@ #include DECLARE_PER_CPU(u64, tlbstate_untag_mask); +#ifdef CONFIG_COALESCE_TLBI +DECLARE_PER_CPU(bool, kernel_cr3_loaded); +#endif void __flush_tlb_all(void); -- 2.51.0