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Fri, 10 Oct 2025 08:20:09 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , , Thierry Reding Subject: [PATCH v1 1/2] spi: tegra210-quad: Fix timeout handling Date: Fri, 10 Oct 2025 15:20:00 +0000 Message-ID: <20251010152001.2399799-2-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251010152001.2399799-1-va@nvidia.com> References: <20251010152001.2399799-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06D:EE_|MW4PR12MB6998:EE_ X-MS-Office365-Filtering-Correlation-Id: 79a06250-f53c-4c3e-37dd-08de08108cbb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yvscNt5jGC5gPKndNDo1yd/LvLKTuxD2seCx6pcM1gt11TNqjvDk+wBtUV5/?= =?us-ascii?Q?BmvyR35ZViUz4oM6Bim7yT44BItvC5nKYiO3ZTe+XV86+Y+IJgbJcD3Xs4Ql?= =?us-ascii?Q?EoAdq03ensT92BRPXovSletIzkR/WrHe69oR/SR8NMIh3Xm9N6ghHf2sFca1?= =?us-ascii?Q?2HR/e75MDUDqTogH8Omk6XlipSPVoJu7zPGO+Sx8zO/K0XWOn28ayRFlXS5p?= =?us-ascii?Q?FPe3ZsPNYQQOGjplbf9EVjj0IkgDmIjrbDE4Qe3fra6nPCzIDRgTyYJU3krh?= =?us-ascii?Q?O/+RbJh4EqXVVbdaAIEOoLCrLtX4U2+GxMXWj5QcsLWkc9tdgOiTEVK6Unja?= =?us-ascii?Q?vHJxY/59xuLZh2cvYtOWQulH7zI3js2x/IHOWz4e5jiSANko2ZymL8qj+p2Y?= =?us-ascii?Q?RmWSTFzk8HJPy/g1uVslrq1sFbnuqiqHAZ+YiFYnO0cVLiuCE8SLmTo8ByVA?= =?us-ascii?Q?PAAJLjcrm1UxbN8boyARFji9g+KRCCqrFREg0d8quOK1lxeA/57zhZzjtsKe?= =?us-ascii?Q?MQHB6oh9fKV6BIfAqdwkPxr4pOGgGL7PrimyQkHCdm3qVg/SREHp3EDlZeDt?= =?us-ascii?Q?0x4LTQRye3ZFj4B00LCOouu+dTYC29k7B66/ngVdZ7gZVsm9T3AcGesUfacg?= =?us-ascii?Q?hYuWfGrLJ6WmkjEpanm5CfISd5L/KHEH/Faz91B2xME0D/wHj6jPDerqhmK1?= =?us-ascii?Q?0gS7g0itJaGWNQqX9Nqo28NsRt9cMd+Tg4+pFPmyd8bdGfS5YvgnzCKF6xks?= =?us-ascii?Q?8iyWWHq4MGdb5HsNXqt4BSWgq0qMko5yj8DlJKK6/891SsncD8xdq/YyHf/B?= =?us-ascii?Q?HkCvW1Lo8I8KclBfM2IfToEb3ADuQqXOGNvKAw5Y28cLIqbCFCw+A6oDBC/U?= =?us-ascii?Q?z/R2xNkoPB2OcMpgc/ffbUApPREgNv1uBlObmcVj0Dzy/EVG75GadJL3R12v?= =?us-ascii?Q?8uhJRH6mVJgsvIj5nascWPUbGJb00nGkoVd+lwwUzHHaFbbKiIJvshnB5Htm?= =?us-ascii?Q?7tMNulyYJv/6CePLyk4pDmIRw+Rwx1DFrPWUd6vj8cy67S82ks9hGEoAR7+n?= =?us-ascii?Q?P7JpgoQJm3LJyRhgAzxH3cB/rgB8TP+833y7ArbMn7EE4JoOwR9+MJ+NX8TE?= =?us-ascii?Q?BK33q48mAXmSF7gLkrrzosprxcyv1qJMPkwWXLPU7Wj83r7+t6bl+d+4ugJ2?= =?us-ascii?Q?LSheNPyd2SCs9HLeJJMaZ8FvW8H0sgHw5VM7VHKnodHS9aJPEY3WcMsCRhD2?= =?us-ascii?Q?nmNxb63RvrRMOAcZO4m7jW8IKm92qNVq4WaHXnkyOL+JG5vOfNXLUTxRAXaX?= =?us-ascii?Q?N7E/FKxaKQE5Aw25UquQeZRH1kfyY6At8tCgAAS4KaKPbD0Tsxqd9rVIPZuW?= =?us-ascii?Q?rff6E547LZWNqHzK/gwUxMHdednccA4rBuiT3c8kfwY5/4fpGpRU+p3AmW02?= =?us-ascii?Q?02FHHBg219kZ40gwZVan3/tpJmbhUl4YIt2vFzmaB3UTdduzVyJ8RTLqEH57?= =?us-ascii?Q?NL4qHOIYI2rO3pLnNeNrvrZiR0rLQhwP9xZ/LLVIEAhlxEflpQ0+KHztHGHZ?= =?us-ascii?Q?R5NK/kOXsEHaDpZYn9c=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 15:20:30.4924 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79a06250-f53c-4c3e-37dd-08de08108cbb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6998 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the CPU that the QSPI interrupt handler runs on (typically CPU 0) is excessively busy, it can lead to rare cases of the IRQ thread not running before the transfer timeout is reached. While handling the timeouts, any pending transfers are cleaned up and the message that they correspond to is marked as failed, which leaves the curr_xfer field pointing at stale memory. To avoid this, clear curr_xfer to NULL upon timeout and check for this condition when the IRQ thread is finally run. While at it, also make sure to clear interrupts on failure so that new interrupts can be run. A better, more involved, fix would move the interrupt clearing into a hard IRQ handler. Ideally we would also want to signal that the IRQ thread no longer needs to be run after the timeout is hit to avoid the extra check for a valid transfer. Fixes: 921fc1838fb0 ("spi: tegra210-quad: Add support for Tegra210 QSPI con= troller") Signed-off-by: Thierry Reding Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index 3be7499db21e..c2f880d08109 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1024,8 +1024,10 @@ static void tegra_qspi_handle_error(struct tegra_qsp= i *tqspi) dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->sta= tus_reg); tegra_qspi_dump_regs(tqspi); tegra_qspi_flush_fifos(tqspi, true); - if (device_reset(tqspi->dev) < 0) + if (device_reset(tqspi->dev) < 0) { dev_warn_once(tqspi->dev, "device reset failed\n"); + tegra_qspi_mask_clear_irq(tqspi); + } } =20 static void tegra_qspi_transfer_end(struct spi_device *spi) @@ -1175,12 +1177,14 @@ static int tegra_qspi_combined_seq_xfer(struct tegr= a_qspi *tqspi, QSPI_DMA_CTL); } =20 - /* Reset controller if timeout happens */ - if (device_reset(tqspi->dev) < 0) - dev_warn_once(tqspi->dev, - "device reset failed\n"); - ret =3D -EIO; - goto exit; + /* Reset controller if timeout happens */ + if (device_reset(tqspi->dev) < 0) { + dev_warn_once(tqspi->dev, + "device reset failed\n"); + tegra_qspi_mask_clear_irq(tqspi); + } + ret =3D -EIO; + goto exit; } =20 if (tqspi->tx_status || tqspi->rx_status) { @@ -1196,6 +1200,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_= qspi *tqspi, goto exit; } msg->actual_length +=3D xfer->len; + tqspi->curr_xfer =3D NULL; if (!xfer->cs_change && transfer_phase =3D=3D DATA_TRANSFER) { tegra_qspi_transfer_end(spi); spi_transfer_delay_exec(xfer); @@ -1205,6 +1210,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_= qspi *tqspi, ret =3D 0; =20 exit: + tqspi->curr_xfer =3D NULL; msg->status =3D ret; =20 return ret; @@ -1290,6 +1296,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct te= gra_qspi *tqspi, msg->actual_length +=3D xfer->len + dummy_bytes; =20 complete_xfer: + tqspi->curr_xfer =3D NULL; + if (ret < 0) { tegra_qspi_transfer_end(spi); spi_transfer_delay_exec(xfer); @@ -1480,6 +1488,15 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, vo= id *context_data) { struct tegra_qspi *tqspi =3D context_data; =20 + /* + * Occasionally the IRQ thread takes a long time to wake up (usually + * when the CPU that it's running on is excessively busy) and we have + * already reached the timeout before and cleaned up the timed out + * transfer. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 15:20:35.1620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63a12abe-17a5-4776-fd98-08de08108f85 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9127 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Under high system load, QSPI interrupts can be delayed or blocked on the target CPU, causing wait_for_completion_timeout() to report failure even though the hardware successfully completed the transfer. This has been observed in production during error injection, RAS firmware activity, and CPU saturation scenarios. When a timeout occurs, check the QSPI_RDY bit in QSPI_TRANS_STATUS to determine if the hardware actually completed the transfer. If so, manually invoke the completion handler to process the transfer successfully instead of failing it. This distinguishes lost/delayed interrupts from real hardware timeouts, preventing unnecessary failures of transfers that completed successfully. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 164 ++++++++++++++++++++++---------- 1 file changed, 114 insertions(+), 50 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index c2f880d08109..757e9fe23e0e 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1019,17 +1019,22 @@ static void tegra_qspi_dump_regs(struct tegra_qspi = *tqspi) tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); } =20 -static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) +static void tegra_qspi_reset(struct tegra_qspi *tqspi) { - dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->sta= tus_reg); - tegra_qspi_dump_regs(tqspi); - tegra_qspi_flush_fifos(tqspi, true); if (device_reset(tqspi->dev) < 0) { dev_warn_once(tqspi->dev, "device reset failed\n"); tegra_qspi_mask_clear_irq(tqspi); } } =20 +static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) +{ + dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->sta= tus_reg); + tegra_qspi_dump_regs(tqspi); + tegra_qspi_flush_fifos(tqspi, true); + tegra_qspi_reset(tqspi); +} + static void tegra_qspi_transfer_end(struct spi_device *spi) { struct tegra_qspi *tqspi =3D spi_controller_get_devdata(spi->controller); @@ -1043,6 +1048,49 @@ static void tegra_qspi_transfer_end(struct spi_devic= e *spi) tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); } =20 +static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi); +static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi); + +/** + * tegra_qspi_handle_timeout - Handle transfer timeout with hardware check + * @tqspi: QSPI controller instance + * + * When a timeout occurs but hardware has completed the transfer (interrupt + * was lost or delayed), manually trigger transfer completion processing. + * This avoids failing transfers that actually succeeded. + * + * Returns: 0 if transfer was completed, -ETIMEDOUT if real timeout + */ +static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) +{ + irqreturn_t ret; + u32 status; + + /* Check if hardware actually completed the transfer */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + if (!(status & QSPI_RDY)) + return -ETIMEDOUT; + + /* + * Hardware completed but interrupt was lost/delayed. Manually + * process the completion by calling the appropriate handler. + */ + dev_warn_ratelimited(tqspi->dev, + "QSPI interrupt timeout, but transfer complete\n"); + + /* Clear the transfer status */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); + + /* Manually trigger completion handler */ + if (!tqspi->is_curr_dma_xfer) + ret =3D handle_cpu_based_xfer(tqspi); + else + ret =3D handle_dma_based_xfer(tqspi); + + return (ret =3D=3D IRQ_HANDLED) ? 0 : -EIO; +} + static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len) { u32 cmd_config =3D 0; @@ -1074,6 +1122,30 @@ static u32 tegra_qspi_addr_config(bool is_ddr, u8 bu= s_width, u8 len) return addr_config; } =20 +static void tegra_qspi_dma_stop(struct tegra_qspi *tqspi) +{ + u32 value; + + if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + + if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + + value =3D tegra_qspi_readl(tqspi, QSPI_DMA_CTL); + value &=3D ~QSPI_DMA_EN; + tegra_qspi_writel(tqspi, value, QSPI_DMA_CTL); +} + +static void tegra_qspi_pio_stop(struct tegra_qspi *tqspi) +{ + u32 value; + + value =3D tegra_qspi_readl(tqspi, QSPI_COMMAND1); + value &=3D ~QSPI_PIO; + tegra_qspi_writel(tqspi, value, QSPI_COMMAND1); +} + static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { @@ -1081,7 +1153,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_= qspi *tqspi, struct spi_transfer *xfer; struct spi_device *spi =3D msg->spi; u8 transfer_phase =3D 0; - u32 cmd1 =3D 0, dma_ctl =3D 0; + u32 cmd1 =3D 0; int ret =3D 0; u32 address_value =3D 0; u32 cmd_config =3D 0, addr_config =3D 0; @@ -1148,43 +1220,28 @@ static int tegra_qspi_combined_seq_xfer(struct tegr= a_qspi *tqspi, QSPI_DMA_TIMEOUT); =20 if (WARN_ON_ONCE(ret =3D=3D 0)) { - dev_err_ratelimited(tqspi->dev, - "QSPI Transfer failed with timeout\n"); - if (tqspi->is_curr_dma_xfer) { - if ((tqspi->cur_direction & DATA_DIR_TX) && - tqspi->tx_dma_chan) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if ((tqspi->cur_direction & DATA_DIR_RX) && - tqspi->rx_dma_chan) - dmaengine_terminate_all(tqspi->rx_dma_chan); - } - - /* Abort transfer by resetting pio/dma bit */ - if (!tqspi->is_curr_dma_xfer) { - cmd1 =3D tegra_qspi_readl - (tqspi, - QSPI_COMMAND1); - cmd1 &=3D ~QSPI_PIO; - tegra_qspi_writel - (tqspi, cmd1, - QSPI_COMMAND1); - } else { - dma_ctl =3D tegra_qspi_readl - (tqspi, - QSPI_DMA_CTL); - dma_ctl &=3D ~QSPI_DMA_EN; - tegra_qspi_writel(tqspi, dma_ctl, - QSPI_DMA_CTL); + /* + * Check if hardware completed the transfer + * even though interrupt was lost or delayed. + * If so, process the completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); + + /* Abort transfer by resetting pio/dma bit */ + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + else + tegra_qspi_pio_stop(tqspi); + + /* Reset controller if timeout happens */ + tegra_qspi_reset(tqspi); + + ret =3D -EIO; + goto exit; } - - /* Reset controller if timeout happens */ - if (device_reset(tqspi->dev) < 0) { - dev_warn_once(tqspi->dev, - "device reset failed\n"); - tegra_qspi_mask_clear_irq(tqspi); - } - ret =3D -EIO; - goto exit; } =20 if (tqspi->tx_status || tqspi->rx_status) { @@ -1275,16 +1332,23 @@ static int tegra_qspi_non_combined_seq_xfer(struct = tegra_qspi *tqspi, ret =3D wait_for_completion_timeout(&tqspi->xfer_completion, QSPI_DMA_TIMEOUT); if (WARN_ON(ret =3D=3D 0)) { - dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer) { - if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan) - dmaengine_terminate_all(tqspi->rx_dma_chan); + /* + * Check if hardware completed the transfer even though + * interrupt was lost or delayed. If so, process the + * completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); + + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + + tegra_qspi_handle_error(tqspi); + ret =3D -EIO; + goto complete_xfer; } - tegra_qspi_handle_error(tqspi); - ret =3D -EIO; - goto complete_xfer; } =20 if (tqspi->tx_status || tqspi->rx_status) { --=20 2.17.1