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Fri, 10 Oct 2025 01:03:39 -0700 From: Zhi Wang To: CC: , , , , , , , , , , , , , , , , , , , , , Subject: [RFC 1/6] rust: io: refactor Io helpers into IoRegion trait Date: Fri, 10 Oct 2025 08:03:25 +0000 Message-ID: <20251010080330.183559-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251010080330.183559-1-zhiw@nvidia.com> References: <20251010080330.183559-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|DS0PR12MB9274:EE_ X-MS-Office365-Filtering-Correlation-Id: 17d903c8-a3a3-4231-ee89-08de07d38cc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Z3XOFPQdNqgbcOv4UaTI56nob718liAtQ89r0o2D2eLXEWdfdklgFnmzOv14?= =?us-ascii?Q?nBuPvXsouv4h9lxrGRXoZrhcBgQ/3+6RcWvz7JLmes7Ui3bpV56e6TlJKc2z?= =?us-ascii?Q?DO9LzA7LsRMJXYKfM7eo3F0p40zxBUuOl+wLWfkdG2+6yhHqaRy3hbjm4cWv?= =?us-ascii?Q?HeojoOWkJTBP9y1+4nfld5qbBD1YoePfBJC4LDLsSAN3fDMGgZBI5WoI7iMx?= =?us-ascii?Q?EbSyJpX3qGzrpQbyda+AJT0yRO99XbxA+oUXKnClKqdP3Wgo8mmjXTo2wE6b?= =?us-ascii?Q?nnd9i4YDusw1n+N8b/VMlQUQRwjEwlXOx4DKooilNxR2EIAD0Y4tlRyK/P/3?= =?us-ascii?Q?y/nHdrJKbkrMqEqU57TocwZE16ihfjrTDgYBxFq63+S8mpXYOuBwAAR5i9Il?= =?us-ascii?Q?APr8gJDLHe7G+s7/KRg8191wCbXDjkphT0R1mhSivaUrdMlkEEQwp+odETZv?= =?us-ascii?Q?FQorW0edPZBsIzbvkoWZQsPDUFRlHBuKDemhI47TCdY7t1T+n+yDpS/2Uv4W?= =?us-ascii?Q?qSEu7C2o6ld2UPptt5VAdPUwVcPtAg7uq5f+cL0zwUlDgzaJbfpyONb2t++E?= =?us-ascii?Q?l2nxtX18EWItP9pgh2KVBl2ICF0uLIn3NL+TtC7w3qw+WfdzWHJvWXhBgxWV?= =?us-ascii?Q?1+O5/eqORc6AXgqemZI/uVLgk/aw2J+fkYeMSwFnrJc87GT7ytlAol+lb3rw?= =?us-ascii?Q?bhgoZOBWDGb791BF8BJl7dx21BMJy418TqhJwLDVzjUd6/jMInsI+cQTtdC7?= =?us-ascii?Q?QBCJOFx8qkigpxen6ykeq6woMr6HDLRONPdPa1relQpmKE9wr9s7DURdYxrO?= =?us-ascii?Q?faRHl5M8hQ5BFM/cFoxAegK2nwJYJ1uwPdl28i87JHwprz8nxzqSEsZXRh97?= =?us-ascii?Q?AEGMS1oPXl9B7BKV1r4wlz/VgFkax16TMlyzrUalkwTVewlQ/apM4PF3gG3E?= =?us-ascii?Q?N42mi9n4N9HSqqaCXOHy+LBffO3T/d4sbG399qbnquX+hqvEgyP1D0qCKDfG?= =?us-ascii?Q?ZaR6d3AbBvv2/VkBp6j+7XLXOz10Y4F4FEl94aL3TZL3m+kluokdFgWahZVe?= =?us-ascii?Q?sYedBZDHBXYi21QN60tUU1buWWg7yiH7r/04wgJA8hfvPhMTWgZ4W/cvmRlN?= =?us-ascii?Q?XjbnxMQpVRchQq4aHsNZdG9i+zL4q8zmzVzw7UPDNIdCAkFfYWMAHJi1EkV0?= =?us-ascii?Q?25mraKEtcXTej4dx/ykzERNu/h4RbCxTtbd4odk1evK8hLJUzoUSSC2LFI+p?= =?us-ascii?Q?fT7SVIeMRVMF5pe27PV3MMsnCtUMwmpcx7RHIdoXCRBfJhnMcckvxoXR+Y4z?= =?us-ascii?Q?qVuLIbKyXYogZlDWqNnI6w3E/w5cLUcmSODo08yvhvdXIMAWLKddtKyyqgaC?= =?us-ascii?Q?jklD1jvoeo5OZg9A5FxcfhGh4FNS95efpEP7XCAc/hLYXEVz2HJpf51f9bdh?= =?us-ascii?Q?UxZnN1VqoXvH7hid2LO6Ka/lFmZXw9qFoVAKxlzFgjGV0SXEYbgtrV2pm1dy?= =?us-ascii?Q?YWqOHoi9aeXALlArslNMH6JPen4Unmq0Ag+n2k0RwqBfKWDaEOglIRTxmB71?= =?us-ascii?Q?0FsKNCfXizGFhb2xVlA=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:51.2977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17d903c8-a3a3-4231-ee89-08de07d38cc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9274 Content-Type: text/plain; charset="utf-8" The existing `Io` implementation embedded utility methods such as `addr()`, `maxsize()`, and offset validation helpers directly on the struct. To allow sharing of I/O region check logic across different region types (e.g. MMIO BARs, PCI config space), move common bound-checking and address arithmetic into a reusable trait. No functional change intended. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 65 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index 03b467722b86..f4727f3b954e 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -171,32 +171,24 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } - } - +/// Represents a region of I/O space of a fixed size. +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +/// +/// Types implementing this trait (e.g. MMIO BARs or PCI config +/// regions) can share the same accessors. +pub trait IoRegion { /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } + fn maxsize(&self) -> usize; =20 + /// Checks whether an access of type `U` at the given `offset` + /// is valid within this region. #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { + fn offset_valid(offset: usize, size: usize) -> bool { let type_size =3D core::mem::size_of::(); if let Some(end) =3D offset.checked_add(type_size) { end <=3D size && offset % type_size =3D=3D 0 @@ -205,6 +197,8 @@ const fn offset_valid(offset: usize, size: usize) ->= bool { } } =20 + /// Returns the absolute I/O address for a given `offset`. + /// Performs runtime bounds checks using [`offset_valid`] #[inline] fn io_addr(&self, offset: usize) -> Result { if !Self::offset_valid::(offset, self.maxsize()) { @@ -216,12 +210,41 @@ fn io_addr(&self, offset: usize) -> Result { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { build_assert!(Self::offset_valid::(offset, SIZE)); =20 self.addr() + offset } +} + +impl IoRegion for Io { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } +} + +impl Io { + /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &IoRaw) -> &Self { + // SAFETY: `Io` is a transparent wrapper around `IoRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } =20 define_read!(read8, try_read8, readb -> u8); define_read!(read16, try_read16, readw -> u16); --=20 2.47.3 From nobody Fri Dec 19 10:35:55 2025 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010049.outbound.protection.outlook.com [52.101.201.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F6027FB31; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:52.8041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17664e80-f31e-430e-e7de-08de07d38da7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4227 Content-Type: text/plain; charset="utf-8" Refactor the existing MMIO accessors to use common call macros instead of inlining the bindings calls in each `define_{read,write}!` expansion. This factoring separates the common offset/bounds checks from the low-level call pattern, making it easier to add additional I/O accessor families. No functional change intended. Signed-off-by: Zhi Wang --- rust/kernel/io.rs | 67 +++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index f4727f3b954e..8d67d46777db 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -112,8 +112,22 @@ pub fn maxsize(&self) -> usize { #[repr(transparent)] pub struct Io(IoRaw); =20 +macro_rules! call_mmio_read { + ($c_fn:ident, $self:ident, $offset:expr, $type:ty, $addr:expr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($addr as *const c_void) } + }; +} + +macro_rules! call_mmio_write { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $addr:expr, $value:ex= pr) =3D> { + // SAFETY: By the type invariant `addr` is a valid address for MMI= O operations. + unsafe { bindings::$c_fn($value, $addr as *mut c_void) } + }; +} + macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + ($(#[$attr:meta])* $name:ident, $try_name:ident, $call_macro:ident, $c= _fn:ident -> $type_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -121,10 +135,9 @@ macro_rules! define_read { $(#[$attr])* #[inline] pub fn $name(&self, offset: usize) -> $type_name { - let addr =3D self.io_addr_assert::<$type_name>(offset); + let _addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(addr as *const c_void) } + $call_macro!($c_fn, self, offset, $type_name, _addr) } =20 /// Read IO data from a given offset. @@ -133,16 +146,17 @@ pub fn $name(&self, offset: usize) -> $type_name { /// out of bounds. $(#[$attr])* pub fn $try_name(&self, offset: usize) -> Result<$type_name> { - let addr =3D self.io_addr::<$type_name>(offset)?; + let _addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - Ok(unsafe { bindings::$c_fn(addr as *const c_void) }) + Ok($call_macro!($c_fn, self, offset, $type_name, _addr)) } }; } +pub(crate) use define_read; =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + ($(#[$attr:meta])* $name:ident, $try_name:ident, $call_macro:ident, $c= _fn:ident <- $type_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile @@ -150,10 +164,9 @@ macro_rules! define_write { $(#[$attr])* #[inline] pub fn $name(&self, value: $type_name, offset: usize) { - let addr =3D self.io_addr_assert::<$type_name>(offset); + let _addr =3D self.io_addr_assert::<$type_name>(offset); =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } + $call_macro!($c_fn, self, offset, $type_name, _addr, value) } =20 /// Write IO data from a given offset. @@ -162,14 +175,14 @@ pub fn $name(&self, value: $type_name, offset: usize)= { /// out of bounds. $(#[$attr])* pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { - let addr =3D self.io_addr::<$type_name>(offset)?; + let _addr =3D self.io_addr::<$type_name>(offset)?; =20 - // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. - unsafe { bindings::$c_fn(value, addr as *mut c_void) } + $call_macro!($c_fn, self, offset, $type_name, _addr, value); Ok(()) } }; } +pub(crate) use define_write; =20 /// Represents a region of I/O space of a fixed size. /// @@ -246,43 +259,47 @@ pub unsafe fn from_raw(raw: &IoRaw) -> &Self { unsafe { &*core::ptr::from_ref(raw).cast() } } =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); + define_read!(read8, try_read8, call_mmio_read, readb -> u8); + define_read!(read16, try_read16, call_mmio_read, readw -> u16); + define_read!(read32, try_read32, call_mmio_read, readl -> u32); define_read!( #[cfg(CONFIG_64BIT)] read64, try_read64, + call_mmio_read, readq -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_read!(read8_relaxed, try_read8_relaxed, call_mmio_read, readb_r= elaxed -> u8); + define_read!(read16_relaxed, try_read16_relaxed, call_mmio_read, readw= _relaxed -> u16); + define_read!(read32_relaxed, try_read32_relaxed, call_mmio_read, readl= _relaxed -> u32); define_read!( #[cfg(CONFIG_64BIT)] read64_relaxed, try_read64_relaxed, + call_mmio_read, readq_relaxed -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); + define_write!(write8, try_write8, call_mmio_write, writeb <- u8); + define_write!(write16, try_write16, call_mmio_write, writew <- u16); + define_write!(write32, try_write32, call_mmio_write, writel <- u32); define_write!( #[cfg(CONFIG_64BIT)] write64, try_write64, + call_mmio_write, writeq <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_write!(write8_relaxed, try_write8_relaxed, call_mmio_write, wri= teb_relaxed <- u8); + define_write!(write16_relaxed, try_write16_relaxed, call_mmio_write, w= ritew_relaxed <- u16); + define_write!(write32_relaxed, try_write32_relaxed, call_mmio_write, w= ritel_relaxed <- u32); define_write!( #[cfg(CONFIG_64BIT)] write64_relaxed, try_write64_relaxed, + call_mmio_write, writeq_relaxed <- u64 ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:53.3248 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be4a10b2-c37c-416d-89db-08de07d38dfd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF9A76BB3A6 Content-Type: text/plain; charset="utf-8" Expose a safe Rust wrapper for the `cfg_size` field of `struct pci_dev`, allowing drivers to query the size of a device's configuration space. This is useful for code that needs to know whether the device supports extended configuration space (e.g. 256 vs 4096 bytes) when accessing PCI configuration registers and apply runtime checks. Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 887ee611b553..7a107015e7d2 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -410,6 +410,12 @@ pub fn resource_len(&self, bar: u32) -> Result { // - by its type invariant `self.as_raw` is always a valid pointer= to a `struct pci_dev`. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:53.4996 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97349583-a175-44dc-2a91-08de07d38e10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6652 Content-Type: text/plain; charset="utf-8" Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI configuration space. The new type implements the `IoRegion` trait to share offset validation and bound-checking logic with MMIO regions. Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 61 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 7a107015e7d2..2f94b370fc99 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -12,6 +12,8 @@ error::{from_result, to_result, Result}, io::Io, io::IoRaw, + io::IoRegion, + io::{define_read, define_write}, str::CStr, types::{ARef, Opaque}, ThisModule, @@ -275,6 +277,65 @@ pub struct Device( PhantomData, ); =20 +/// Represents the PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). The actual size is obtained +/// from the underlying `struct pci_dev` via [`Device::cfg_size`]. +pub struct ConfigSpace { + pdev: ARef, +} + +impl IoRegion for ConfigSpace { + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size() as usize + } +} + +macro_rules! call_config_read { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr) =3D> {{ + let mut val: $ty =3D 0; + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset= as i32, &mut val) }; + val + }}; +} + +macro_rules! call_config_write { + ($c_fn:ident, $self:ident, $offset:expr, $ty:ty, $_addr:expr, $value:e= xpr) =3D> {{ + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $offset= as i32, $value) }; + }}; +} + +#[allow(dead_code)] +impl ConfigSpace { + /// Return an initialized object. + pub fn new(pdev: &Device) -> Result { + Ok(ConfigSpace { + pdev: pdev.into(), + }) + } + + define_read!(read8, try_read8, call_config_read, pci_read_config_byte = -> u8); + define_read!(read16, try_read16, call_config_read, pci_read_config_wor= d -> u16); + define_read!(read32, try_read32, call_config_read, pci_read_config_dwo= rd -> u32); + + define_write!(write8, try_write8, call_config_write, pci_write_config_= byte <- u8); + define_write!(write16, try_write16, call_config_write, pci_write_confi= g_word <- u16); + define_write!(write32, try_write32, call_config_write, pci_write_confi= g_dword <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// # Invariants --=20 2.47.3 From nobody Fri Dec 19 10:35:55 2025 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013023.outbound.protection.outlook.com [40.93.196.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CFF527FB0E; Fri, 10 Oct 2025 08:03:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.23 ARC-Seal: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:54.3028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a9448c8-40a3-4a67-21a5-08de07d38e93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8438 Content-Type: text/plain; charset="utf-8" Add a safe wrapper for `pci_find_ext_capability()` that returns an `Option` indicating the offset of a given PCIe extended capability. This allows Rust drivers to query extended capabilities without dealing with raw pointers or integer return codes. The method returns `None` when the capability is not present. Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 2f94b370fc99..5d9c5eef5c85 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -477,6 +477,13 @@ pub fn cfg_size(&self) -> i32 { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. unsafe { (*self.as_raw()).cfg_size } } + + /// Find the extended capability + pub fn find_ext_capability(&self, cap: i32) -> Option { + // SAFETY: `self.as_raw()` is a valid pointer to a `struct pci_dev= `. + let offset =3D unsafe { bindings::pci_find_ext_capability(self.as_= raw(), cap) }; + (offset !=3D 0).then(|| offset as u16) + } } =20 impl Device { --=20 2.47.3 From nobody Fri Dec 19 10:35:55 2025 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013005.outbound.protection.outlook.com [40.93.201.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D7C72836B1; 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Date: Fri, 10 Oct 2025 08:03:30 +0000 Message-ID: <20251010080330.183559-7-zhiw@nvidia.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251010080330.183559-1-zhiw@nvidia.com> References: <20251010080330.183559-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|DS5PPFA3734E4BA:EE_ X-MS-Office365-Filtering-Correlation-Id: ad0c8f16-1326-4388-0aec-08de07d3904e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Oqpt3Y4ynSQXhoaFli+42jDGZxVuBQWE4rzU/8XLdXriAEpFXeazhsjwPszT?= =?us-ascii?Q?BrIzv+zwnmcjzzM5AmjzX9a4JVoOeRxX27WPjOqGliPQCAx3pe7j1By+sjny?= =?us-ascii?Q?Cg+KVA4xA1LWCjRf/q3vdKjseakMH1B2WLfdSNf9xPzfIMvQmfzi2cFYectR?= =?us-ascii?Q?TmgShbefybXtrLKCR/VTtgVZXYveEoIbmV+n0dUM47YeNwcanANtEAJOMUWP?= =?us-ascii?Q?JHHACbVR2cm2XE/CSG188DtvUYy2kmVoKctJPmjTJFePgaSVZIBPo1J4VC0s?= =?us-ascii?Q?Q5dMQavRHDqBD5fxdzVnOsTaguuI635dLhrW189wUC8BOENUFAlSn1GZ0xcZ?= =?us-ascii?Q?iQcxh32S4v17/RVMmxVWmouS9yAZd1ohqYrQQbfpwyFlstOSlsd1Q+uxlU9j?= =?us-ascii?Q?3OmG+AiLC+fjc90DfSXGBxAR3s6bIAICs3hD/7/V8u58iECr68KATNPk66QV?= =?us-ascii?Q?x5NzMsyGiGTlDd0UEi7Hi7wpWJxZo8FE4ZPYa2lm0EfQ5eXhYISkIpK/ZUEG?= =?us-ascii?Q?VyOWKQC1cZfkmF0JngYXgJR2Ij1iDreKrerNUdiLj2oL1f6qMfD+0UPKMl9A?= =?us-ascii?Q?QcZ9xLBjBY37jg4KawzIF94H6d5c/uFSaVizBR7QIEWnWoSxBRK/WfVCGz2r?= =?us-ascii?Q?G2GT+7KU0lpdp7UMbnN+idAPZa4AptA/A5GKttOASLBJfSMiSichp2oEl18H?= =?us-ascii?Q?l90ZJtQ8jWfUWiFoIXcvSpDNJ7Dze0GT+mv4xciCEyBMpgOLkk6nXOQag5FZ?= =?us-ascii?Q?rkkUI2o8lOC8krdllMkZvdWLLANSI8wTk+fWGdRUtkD9Imr9EnaQH1x804zv?= =?us-ascii?Q?gt66wJMKZc+tCO1m4d/CzrQnVNwA+Y+jCX3ZgW08jejNYNeBhg8e1MNSWeIa?= =?us-ascii?Q?m5OSMCQf7Mb29557omz+GfMJC7gvfLK8PMBSJ/3gjKioFgIPDYaa9QpIMVyn?= =?us-ascii?Q?n/Xx6vXY8oGQZo6u950us+R8onEOKbq+mEtCE3tVtkQxl2/lhiTSIbwboEdV?= =?us-ascii?Q?dMIZ1N6RPxyiJo+EDrwNu4jvHfc1SNNYYDF7v01soL9v/HqXQE+TRxvaF7nA?= =?us-ascii?Q?fQT13gPsvmofi6Bj24GXfrwsI5sN4Y4aGCFC476O8qxSr92TcuMWNzKlogLi?= =?us-ascii?Q?8fzZwEWtGU4SG1mPYsw3LcZV+udn3dp+ATNRUzRiadIzE81zqhi44F7mHSI+?= =?us-ascii?Q?7kKgoqVta5sG/Dn4EcFPBSNMIDsPY7vLWf0W/lmZI61KVntp5EjqLhkd0cwo?= =?us-ascii?Q?oPK6VUog8x4Xrm4/Jk+tapitk4+Qc7KDJXwXQrCJvl0EA2Vl2cD6A3FQIWpr?= =?us-ascii?Q?efhwepsQHbqyC1czxw0oX7Y5u8STaKw17vak/T5d/kKLvRVl6FVXDOjLhT3r?= =?us-ascii?Q?CCxuXmiwf4XjcjUXiIhcTDj8BbX/BDWizCEgkZ0r/nzATrXLoR5eaEtPwHDW?= =?us-ascii?Q?1a8voMVVjAPGF+VByCKtlbDYYZ8q/zDae1WlFJnrgAzp9YjG2Q2xcfgX4kLz?= =?us-ascii?Q?LNVv3Y7T+Reh6qIGm5le8/knBUAevMql3CYkgl8ipP9BeRL5Psq6m2jq/NgL?= =?us-ascii?Q?0ZrLaGEFEgrxKSxkurM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 08:03:57.2653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad0c8f16-1326-4388-0aec-08de07d3904e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFA3734E4BA Content-Type: text/plain; charset="utf-8" Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/driver.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 1380b47617f7..605d9146113c 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -44,6 +44,10 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo)= -> Result::new(pdev)?; + + dev_info!(pdev.as_ref(), "Nova Core GPU driver read pci {:x}.\n", = config.read16(0)); + let this =3D KBox::pin_init( try_pin_init!(Self { gpu <- Gpu::new(pdev, devres_bar, bar), --=20 2.47.3