From nobody Fri Dec 19 12:18:27 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D08E827AC31; Fri, 10 Oct 2025 08:03:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760083406; cv=none; b=thYMi3Gv3sA06fpoWM8UBBqNOhqeJLn804lBw3Az3gq2CxCe5B1UthzJ5V5roz7bpy3t7hg1zEpDGyg7vH8FsD/a+b0tCZ7Dw1TSRIaXgVKkKYfEe4lNaS4XT01udFmFcjpzp0pGtCeN13CYJNADILPnNdzz3MU4szfzcZ3UOjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760083406; c=relaxed/simple; bh=3uQ+hglIqHXJTJg+gQ6Yg+4ETaiQ+eeaaAdy0Jp4ITM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K6Ns3o2fXSGHFlhqki4tK9cWfdL5jHnUua0fFkLv9Qgy7If1JBc26QQEGqJABxjZBWTvlwn97RcA6JUyzqwDUJJd6JpsuCc3G7DAq1RSqFJcLoq6kyno0lIs2hG2HrQ65WhLCf3PJKuF142ryjtOwjB857W/y6i7SsLGDkngir0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 10 Oct 2025 16:03:16 +0800 Received: from aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 10 Oct 2025 16:03:16 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH v2 3/3] watchdog: aspeed: Add support for AST2700 platform Date: Fri, 10 Oct 2025 16:03:15 +0800 Message-ID: <20251010080315.816628-4-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251010080315.816628-1-chin-ting_kuo@aspeedtech.com> References: <20251010080315.816628-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AST2700 platform support to the ASPEED watchdog driver. This includes a new per-platform configuration with SCU reset status register at SCU1_070 and support for 5 reset mask registers. Signed-off-by: Chin-Ting Kuo Reviewed-by: Guenter Roeck --- drivers/watchdog/aspeed_wdt.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index d23e565f30a8..c9e79851504c 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -83,10 +83,24 @@ static const struct aspeed_wdt_config ast2600_config = =3D { .num_reset_masks =3D 2, }; =20 +static const struct aspeed_wdt_config ast2700_config =3D { + .ext_pulse_width_mask =3D 0xfffff, + .irq_shift =3D 0, + .irq_mask =3D GENMASK(31, 10), + .scu =3D { + .compatible =3D "aspeed,ast2700-scu0", + .reset_status_reg =3D 0x70, + .wdt_reset_mask =3D 0xf, + .wdt_reset_mask_shift =3D 0, + }, + .num_reset_masks =3D 5, +}; + static const struct of_device_id aspeed_wdt_of_table[] =3D { { .compatible =3D "aspeed,ast2400-wdt", .data =3D &ast2400_config }, { .compatible =3D "aspeed,ast2500-wdt", .data =3D &ast2500_config }, { .compatible =3D "aspeed,ast2600-wdt", .data =3D &ast2600_config }, + { .compatible =3D "aspeed,ast2700-wdt", .data =3D &ast2700_config }, { }, }; MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); @@ -483,7 +497,7 @@ static int aspeed_wdt_probe(struct platform_device *pde= v) } =20 if (!of_device_is_compatible(np, "aspeed,ast2400-wdt")) { - u32 reset_mask[2]; + u32 reset_mask[5]; size_t nrstmask =3D wdt->cfg->num_reset_masks; u32 reg =3D readl(wdt->base + WDT_RESET_WIDTH); int i; --=20 2.34.1