From nobody Fri Oct 10 19:58:11 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C690B273D66 for ; Fri, 10 Oct 2025 07:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760079653; cv=none; b=lV0RzTor7WH9YX5C7dNNQATpGx7aw5G00aaJ6UJPDuyIS9uz7xtj1dbAvyud5ZzGrsRVXmdPs+rOGIiXvXFsPh/5GejWy6SUJOp/5/E/5FGNVOAZBmTCTXIg2mnV5ZprrpDWLiNBhGLlmF1ofRvKHNrDAYK9Y1zU/Y1Q2QmF+XM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760079653; c=relaxed/simple; bh=O0biSYrW/9XxBFmxHKrPgsN5287YHIbCdKGtZoZQSR8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=eZA54IfFdI2Ljo++NqD8mjgaWL4oB4r9fsrS3WOGh6NQtk71UoFsUFv8cYxhNY5RECdyxi6BVBMLfywljF2CrHENMvLIlogTXnbjOKovnQHAefwn4RrcorbWSaL8Yh4FrdcxZacQm3cjPZ5Lyl5cQ27lmopmjYm1+L+UzTDb/yY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=jZUhDbi1; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="jZUhDbi1" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20251010070049epoutp0428fa116b661edd13d8ef24bbad0e62c4~tDx3HxyQK0153001530epoutp04d for ; Fri, 10 Oct 2025 07:00:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20251010070049epoutp0428fa116b661edd13d8ef24bbad0e62c4~tDx3HxyQK0153001530epoutp04d DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1760079649; bh=fCbewzaUwqGlVCzA6eYiuf1FPSZzQPmbJ+4dCqnOFFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jZUhDbi1Ik4DlRfWqQNL/Tit5I8rdnJL4V/pUjoHT2Wp9ItmxmqxYNpyxpvgk7D9J q4qqRHBiNUiR+UOip1mTqTmve7+pngYfefkQreeHHBwTx1sz+dk6IQae76jFStskAn EMBf7T14chTjuDwtxpNMJmtg1xBxg4i/ggI/OR/k= Received: from epsnrtp03.localdomain (unknown [182.195.42.155]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPS id 20251010070049epcas5p2dfa2863435e504318fb840a1930bc0a9~tDx2keHDs2760227602epcas5p2e; Fri, 10 Oct 2025 07:00:49 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.87]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4cjd1X2PsSz3hhT4; Fri, 10 Oct 2025 07:00:48 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20251010070047epcas5p2c6f0fa406b15f10b74430251b41df3ce~tDx1Fq9A82285922859epcas5p2E; Fri, 10 Oct 2025 07:00:47 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20251010070043epsmtip241e0a538a7bd7369cc9dd9acd647cc89~tDxwuTGtH0784907849epsmtip2O; Fri, 10 Oct 2025 07:00:42 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, johan@kernel.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v9 2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Date: Fri, 10 Oct 2025 12:39:08 +0530 Message-Id: <20251010070912.3758334-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251010070912.3758334-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20251010070047epcas5p2c6f0fa406b15f10b74430251b41df3ce X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20251010070047epcas5p2c6f0fa406b15f10b74430251b41df3ce References: <20251010070912.3758334-1-pritam.sutar@samsung.com> Enable UTMI+ phy support for this SoC which is very similar to what the existing Exynos850 supports. Add required change in phy driver to support HS phy for this SoC. Reviewed-by: Alim Akhtar Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 123 ++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 125 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index a88ba95bdc8f..dfc2cc71e579 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -2054,6 +2054,126 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* Bypass PHY isol */ + inst->phy_cfg->phy_isol(inst, false); + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret =3D regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_usb20_regulators[] =3D { + "dvdd", "vdd18", "vdd33", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] =3D= { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = =3D { + .phy_cfg =3D phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb20_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2380,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-phy", + .data =3D &exynosautov920_usbdrd_phy }, { }, }; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 71e0c09a49eb..4923f9be3d1f 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -688,4 +688,6 @@ #define GS101_GRP2_INTR_BID_UPEND (0x0208) #define GS101_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* exynosautov920 */ +#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1