From nobody Fri Dec 19 12:21:31 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80B8A2FCBFC; Fri, 10 Oct 2025 18:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120767; cv=none; b=ZxIRkuQjZRTM0u9UjXMBU71oZr6pIMNw29RosDCv33WU0MMohq2jdHfXCmZEsBKH70FTEhNYjnXAsQN5WsGDvzMSRGzinbUOAu/8+nvzkQJxvkfGY5NIJc48woFlcjr4V8HZPi9GZ0hVx9xYgzu3b/lOabUGdQURMCwuvMlh94Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120767; c=relaxed/simple; bh=TGBu5VD9Csx9auQIJRtZcEAMf9PQUb4RlRSBX/JW7Fs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qNHYkTwizn3JIGE8pft6h4QxL+z54B0RqiJfuaOWV++L+zRLfkg7hs6g9jGa/FnmRCyFIMSa+m8dfuJEO1fj1/c2OAvPQC9ztOV/frHg5cyxEcNhcs5k6DkScZ7hV9RUI8NJaMCGL3poWSmDffV1ShAEFDjqCFb0C9IcRLIB5gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A715CC113D0; Fri, 10 Oct 2025 18:26:06 +0000 (UTC) From: Manivannan Sadhasivam Date: Fri, 10 Oct 2025 11:25:47 -0700 Subject: [PATCH 1/3] dt-bindings: PCI: Update the email address for Manivannan Sadhasivam Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-pci-binding-v1-1-947c004b5699@oss.qualcomm.com> References: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> In-Reply-To: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abraham I , Bjorn Andersson , Krishna Chaitanya Chundru Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11583; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=TGBu5VD9Csx9auQIJRtZcEAMf9PQUb4RlRSBX/JW7Fs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBo6U+95cPnia/TtHbTXZqLu/z4crjkktocHrE3u HCxv4o/2dWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaOlPvQAKCRBVnxHm/pHO 9cg4B/0baky/LH238kGsOfDu1EIHw3HtZr5nnWKhyy+LNUApTpGlQLeUHVwdPUAIyj5MOIPB/4U mTx4RrzD57u5wVjBnWFcq94skFiYbSxJtw6NpxWpVsqBNxU95L5hbe19HNaM+2yRqf4+nSDfiFc TwsGzRbXDRBa6GLIVjnbHJudEHyFCDL4UTt78h9oqRpNRRzLcl3daGe4Sbz96cw/4/TqZb2LMAe U6cV3N3G/bEfta2Fik44uIFoG7AF5Q/3dvugBaYF9I0O23GmWtEZHHj+IByr+Q6YQeBYuOhbgBO ccOtuNDfaRUC6FfLUvts6geL/34WmGWIDze5if/SPX5NPruY X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 My linaro email id is no longer active. So switch to kernel.org one. Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentat= ion/devicetree/bindings/pci/pci-ep.yaml index 1868a10d5b10dbffcbf14b5737e51353f55b98d8..baeb583e0bcd708f219071c5b66= a7e2e967299ac 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -11,7 +11,7 @@ description: | =20 maintainers: - Kishon Vijay Abraham I - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 properties: $nodename: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index ab2509ec1c4b40ac91a93033d1bab1b12c39362f..77f8faf54737e0fab089a368976= 290dece4f2e7d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI Express Root Complex Common Properties =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 properties: reg: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index ac3414203d383bbd1a520dc11f317a5da9ca33e4..bed9a40b186bcf2cf93bdf354bd= daa257d229f16 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PCIe Endpoint Controller =20 maintainers: - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml index bdddd4f499d18689db264adf71b41bb43d35cb36..1f2d098b86384014dbd61c6d0e2= bd4a596f3c780 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml @@ -8,7 +8,7 @@ title: Qualcomm SA8255p based firmware managed and ECAM com= pliant PCIe Root Comp =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SA8255p SoC PCIe root complex controller is based on the Synops= ys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index 19afe2a03409b8f638e0f4a3deda304e397ab9f7..dca84580f0da00ed36e34d83bbf= 8aedf0c180f8b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -8,7 +8,7 @@ title: Qualcomm SA8775p PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SA8775p SoC PCIe root complex controller is based on the Synops= ys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 4d0a915566030f8fbd8bf83a9ccca00fbc7574bd..4238612dd2ce6411f0ec3796682= 868a556724bd7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC7280 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml index 34a4d7b2c8459aeb615736f54c1971014adb205f..6a7c410c9fc30f0644da19a9002= e0d26813731b8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC8180x PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SC8180x SoC PCIe root complex controller is based on the Synops= ys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml index 15ba2385eb73c4e69d6de7dc09cf639bc800f7f2..a18cba10aceaec42e0b105f76c9= 2a82a926d727a 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC8280XP PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synop= sys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml index 26b247a41785fa3e001f7ced165747ac256f0c02..b772e7e6a9e3dda04b990e004db= 446159a766410 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8150 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml index af4dae68d50873bf0e64d47571760b62263594cf..ecc4b971ea490b89894dfd7d334= f718dec57576d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8250 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml index dde3079adbb3312f46d9c0e9cee5abbd67bcab1b..6c109b30ccc61e47568fdabfff9= a4e8a67946f33 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8350 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index 6e0a6d8f0ed070a98560d3e343f14e39b3cf9cd5..2725f849121b56953ccdac26ff8= 134dbae1a39bc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8450 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 38b561e23c1fda677ce2d4257e1084a384648835..f6f7e5330d59c1a20281cc8a869= 91c8720ceefa2 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8550 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is bas= ed on diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index 61581ffbfb2481959344490e54daea001aaa4ca3..2ebf48542911fda6fef91ea43e7= b658b6cdc01e1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -8,7 +8,7 @@ title: Qualcomm X1E80100 PCI Express Root Complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is b= ased on diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 0e1808105a8196b450bacd6fd3d986c67e5e0082..c61930441be09d02c1b83782835= 061b92331560b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex =20 maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam =20 description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare --=20 2.48.1 From nobody Fri Dec 19 12:21:31 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F39B2FD1C3; Fri, 10 Oct 2025 18:26:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120768; cv=none; b=UTQGTY0FUn7uWa1ElkAkeJqX1F5ol07kRjLi7vK6Q/nL2Uxp07hG1FStdYGFRFaz3trlEQ6HRFirgcC09WbUDvfIktKsZqalmxTsgIlVo5L8Y2UrGoD1PBr8f8LR3PPS2YXSw2bmYrECMCUiS5ZqvtUvJGIOFoJ5xZWPwxxZITQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120768; c=relaxed/simple; bh=/aRq5DE/FVItXdRivR/J1AsysvS55h/HwYPYIpjLtxs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GiKAiN5h6lMTfI2o3DNdLtAVjEcesYwhGZLU7K0vuTsfneQoV5j/VhB9GC3uYt102m5TLbcE93LaiAZfKZloWVIlSx99iURtHu2908FUlAkeIcs1Jsmi48nfseYzC4Dy0YE/SydBEMdU/L60UGUqqGLnDdJMT5J9WRFc86CZpnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8779CC19422; Fri, 10 Oct 2025 18:26:07 +0000 (UTC) From: Manivannan Sadhasivam Date: Fri, 10 Oct 2025 11:25:48 -0700 Subject: [PATCH 2/3] dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-pci-binding-v1-2-947c004b5699@oss.qualcomm.com> References: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> In-Reply-To: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abraham I , Bjorn Andersson , Krishna Chaitanya Chundru Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2265; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=/aRq5DE/FVItXdRivR/J1AsysvS55h/HwYPYIpjLtxs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBo6U+9VbUO2gwKKLYys5f6gRb/B/W8XsL1AY9mZ mlkguOiKJWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaOlPvQAKCRBVnxHm/pHO 9QeDB/9UqREHY0Jsj6N7L6hrQU4zbgouIU1ekold6aVoNYkTJY3Nans8es//ZD/zT3/xOPIP9wq qE3XPQBeEl7T1Jh//yZV5rSuDU3cBJpctenuiaqHMGwnRTWzODAFkfJmC9WacbnrNneb9OZYyIc hZdGXD4eHd/3FZ016iy3d7AlXs+h7QoCBd1YOT2GPoBbGr9sUd4AZjt8WEdLEuVBTTzBSCsYBln wH0BxC98L3pduVs2QJHej1rEx3gBUzEwcgUl+0Td6kQjv7Uk8hIWSmMjhWgtA4exDqs7Zx0FLbz xt9HkrPO2y2tB1cdIkAVHn0MN1Nd+H2Dah4OhSVf5Cz2/C98 X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Currently, the binding supports specifying the PHY, PERST#, WAKE# properties in two ways: 1. Controller node (deprecated) - phys - perst-gpios - wake-gpios 2. Root Port node - phys - reset-gpios - wake-gpios But there is no check to make sure that the both variants are not mixed. For instance, if the Controller node specifies 'phys', 'reset-gpios', 'wake-gpios' or if the Root Port node specifies 'phys', 'perst-gpios', 'wake-gpios', then the driver will fail as reported. Hence, enforce the check in the binding to catch these issues. It is also possible that DTs could have 'phys' property in Controller node and 'reset-gpios/wake-gpios' properties in the Root Port node. It will also be a problem, but it is not possible to catch these cross-node issues in the binding. Reported-by: Konrad Dybcio Closes: https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970= ced@oss.qualcomm.com Suggested-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Reported-by: Krishna Chaitanya Chundru --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 77f8faf54737e0fab089a368976290dece4f2e7d..6eaecf83d6efd37e9acb044049c= 1ef95611cbf58 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -111,6 +111,16 @@ patternProperties: phys: maxItems: 1 =20 + oneOf: + - required: + - phys + - reset-gpios + - wake-gpios + - properties: + phys: false + reset-gpios: false + wake-gpios: false + unevaluatedProperties: false =20 required: @@ -129,6 +139,16 @@ anyOf: - required: - msi-map =20 +oneOf: + - required: + - phys + - perst-gpios + - wake-gpios + - properties: + phys: false + perst-gpios: false + wake-gpios: false + allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# =20 --=20 2.48.1 From nobody Fri Dec 19 12:21:31 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AACB2FD7DD; Fri, 10 Oct 2025 18:26:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120769; cv=none; b=skcjS6GxR7UUvl8yzvcj4U4IvK2p2pgqEA/CFVG5h/6C3JWZrprREmHLLxvHQxuEyFAmj6wBDgGHADDljSBlWSWlHZ3CfCvEGQJ4ldeM/yY1ZUp71szTdbIdBQs0daDgwX8sY23Dj7Y9s59dfyGodSaTfkDOYOnMZVh+rxiUs1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760120769; c=relaxed/simple; bh=pv2BzdMiDcx5mA6iDiHhMRhod6ykyXxVkx7QlBdz8s4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kYikHVxtDttKqW4x//HFgma5LYFcA9RdgbCo3N/K252gwX46+yytbvtyev7HwqS5G4+8bagIpOj+mnmxBJqpDhGKHoBcrg3CrgvRXR1UDhJ7mZR+7rol8JAaBcDH+1jOBH357AX+tV7PHpP1f8wyzPHD4IBOh1r9EqTj0eZe01k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D5F5C116D0; Fri, 10 Oct 2025 18:26:08 +0000 (UTC) From: Manivannan Sadhasivam Date: Fri, 10 Oct 2025 11:25:49 -0700 Subject: [PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-pci-binding-v1-3-947c004b5699@oss.qualcomm.com> References: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> In-Reply-To: <20251010-pci-binding-v1-0-947c004b5699@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abraham I , Bjorn Andersson , Krishna Chaitanya Chundru Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1590; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=pv2BzdMiDcx5mA6iDiHhMRhod6ykyXxVkx7QlBdz8s4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBo6U+9/pmvF/0/iMFkn4KsRGiXzoc2/ZoKzqajQ Pz5Kza93ROJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaOlPvQAKCRBVnxHm/pHO 9ZLKB/9ySihbtl5s3z7AJTC+NHAWOU+c+b3SOe3+gOhoPw6sTCgYueTHjcYC0kE/6EQ7kycN0st AdsUMqwhgJW/mA+VhN0P3hS9XR06Fu5mS+TpXIID+OSiJs5DcOlKueNL/Tn8kla4w0PtgJUobuR 2tFdzxyUZDPQG9hcM4ExCwC5JmT22aDVTgkvQ02tRwUf+KFeBW65uqHs3tEerSqt2oZ/T8szHqk zajLFePJBtHpzMUZICmmsHM/fCR0GTrSlkFS4BZFyg7iJQpF3U07fYyvdojbY/k0aXULLNBPXKB 6ITOj6AYBpFhlCKzkHmqsdXfuYm2wyjtTtSHri++3qpa/Nss X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Even for the new DT binding where the PHY and PERST# properties are specified in the Root Port, both are optional. Hence, treat them as optional in the driver too. If both properties are not specified, then fall back to parsing the legacy binding for backwards compatibility. Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port = binding") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd= 2f626f8f53920 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *p= cie, struct device_node *node =20 reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), "reset", GPIOD_OUT_HIGH, "PERST#"); - if (IS_ERR(reset)) + if (IS_ERR(reset) && PTR_ERR(reset) !=3D -ENOENT) return PTR_ERR(reset); =20 - phy =3D devm_of_phy_get(dev, node, NULL); + phy =3D devm_of_phy_optional_get(dev, node, NULL); if (IS_ERR(phy)) return PTR_ERR(phy); =20 + /* + * If both PHY and PERST# properties are not specified, then try the + * legacy binding. + */ + if (PTR_ERR(reset) =3D=3D -ENOENT && !phy) + return -ENOENT; + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; --=20 2.48.1