From nobody Fri Dec 19 14:09:17 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97D2A303CAA; Fri, 10 Oct 2025 20:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129301; cv=pass; b=TD4c1Okg3GbMzllRnGzwyarewGO+DBFq82jy8+yqjuJi3rG5w2EExZy9vzvd5BxDwIBokUi7vq6ltkHT8jXbblUsid9uoftAS9POR/x2pbOBHH0BisyV5HJ0kMQqNBjQL6MObTI59ZDXze5BGfmlp2EoY9DqlL6XdnErita4l0c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129301; c=relaxed/simple; bh=DqdxqtZA+JTQXfSgoa0iFFT+t9Xu2GNK7V17jWtmqQQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JPq3bXmHihrGdTWoMBy51LVlP+fcXA/GkYSQrC20eb1nrrHlp+GD8cyrs0ksteFn2qfJQQUrIGuLSTb/tRZz7/CTXVgl3hTI8foqvLklntThogPuTGK75r5OgkhKaEx1nyhwFJDoUn/EXmC11MmjsvkC7eGCO9wiTwG9hcWfq5s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=QQFrYdfr; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="QQFrYdfr" ARC-Seal: i=1; a=rsa-sha256; t=1760129277; cv=none; d=zohomail.com; s=zohoarc; b=FRB1JV3sOZSZ9JTFNpfXOd2Bv8HgJlwn+Mwuqs0hNoS0vUgHnNLQABUEEvKPwxcqs3HP2vmQ3oQMjStn/fgxJRPyISByAOhp0A9TUlyDa/TrDgVilXzXGq+intdCBoZ3w57VhUXsOh1XOFsBzEc53ExgQcY0v0xuAc+R2Mrpcz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129277; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=bZycTGcqflUTi8jckNmrkgc5LMZTQ/XWz04YrmhHY6Q=; b=lPEXIiqFJRpWR/7jKD5QtjKQUs4Ld6oAxVW7o3FszBl6VucePAMws4ilY0NR9aifc6ohf+PoaBfg3CzSMl/Qn9G+oTxjoRC6PfQOWb7K+1sipM2PS95sX/fZWFFhXfvdOblKxw4aTR8ly/xPgyY5/w3O6DXA4nBzQ7nvA2RTGEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129277; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=bZycTGcqflUTi8jckNmrkgc5LMZTQ/XWz04YrmhHY6Q=; b=QQFrYdfrOeZ1cCsQWfyZDKWD1n7ctc7DQvvMPQyevQLJBwGe9xZFN4Vs+bXqE/5/ fZO2UAwhibKoElCFigRrflEaoUKfPSpInZ21hGxZah1FYWs9YS3c9HmqH7lYJ/ZczqU lQt3qv7b6VjE6k/GklM2bYNOZ5AsuHzZp83XWW3A= Received: by mx.zohomail.com with SMTPS id 1760129275139615.3748636428318; Fri, 10 Oct 2025 13:47:55 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:13 +0200 Subject: [PATCH v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-5-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 All the MFGPLL require MFG_EB to be on for any operation on them, and they only tick when MFG_EB is on as well, therefore making this a parent-child relationship. This dependency wasn't clear during the initial upstreaming of these clock controllers, as it only made itself known when I could observe the effects of the clock by bringing up a different piece of hardware. Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it when initialising the pll to then translate it into the actual CLK_OPS_PARENT_ENABLE flag. Then add the mfg_eb parent to the mfgpll clocks, and set the new PLL_PARENT_EN flag. Fixes: 03dc02f8c7dc ("clk: mediatek: Add MT8196 mfg clock support") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-mt8196-mfg.c | 13 +++++++------ drivers/clk/mediatek/clk-pll.c | 3 +++ drivers/clk/mediatek/clk-pll.h | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index 8e09c0f7b7548f8e286671cea2dac64530b8ce47..a317183f1681bc6e8167c44b2bb= e4a78566ba639 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -58,24 +58,25 @@ .pcw_shift =3D _pcw_shift, \ .pcwbits =3D _pcwbits, \ .pcwibits =3D MT8196_INTEGER_BITS, \ + .parent_name =3D "mfg_eb", \ } =20 static const struct mtk_pll_data mfg_ao_plls[] =3D { - PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0, - BIT(0), MFGPLL_CON1, 24, 0, 0, 0, + PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, + PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22), }; =20 static const struct mtk_pll_data mfgsc0_ao_plls[] =3D { PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, - MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0, - MFGPLL_SC0_CON1, 0, 22), + MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24, + 0, 0, 0, MFGPLL_SC0_CON1, 0, 22), }; =20 static const struct mtk_pll_data mfgsc1_ao_plls[] =3D { PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, - MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0, - MFGPLL_SC1_CON1, 0, 22), + MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24, + 0, 0, 0, MFGPLL_SC1_CON1, 0, 22), }; =20 static const struct of_device_id of_match_clk_mt8196_mfg[] =3D { diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index c4f9c06e5133dbc5902f261353c197fbde95e54d..0f3759fcd9d0228c23f4916d041= d17b731a6c838 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -359,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, =20 init.name =3D data->name; init.flags =3D (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; + if (data->flags & PLL_PARENT_EN) + init.flags |=3D CLK_OPS_PARENT_ENABLE; + init.ops =3D pll_ops; if (data->parent_name) init.parent_names =3D &data->parent_name; diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f6493699c4e367b45038ceede9565ae42a030b47..f49dc2732ffee50ebf023c01b51= 3d74989a6ec7b 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -19,6 +19,7 @@ struct mtk_pll_div_table { =20 #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) +#define PLL_PARENT_EN BIT(2) #define POSTDIV_MASK GENMASK(2, 0) =20 struct mtk_pll_data { --=20 2.51.0