From nobody Fri Dec 19 12:16:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EA0B301473; Fri, 10 Oct 2025 20:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129289; cv=pass; b=pZYK0JPOFDCVwJPi2MpP7EhcdPpcojsp+dxIGwQseHtYvsV4ZQHYeOZdpPSW8JaATRDbsTSyVIupB300T718g6HWoWYHyG9xaRiwfqvUH3rvWkGOpUmPcl6pPlsl702Zxp8nmMOHfH+HZps3sPdOEha4vxLP8vY3XYIHr26COV0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129289; c=relaxed/simple; bh=cLuLu5AbyJVxiyt0gNcL6gvKI2KXKXOQe4f3O/dFThU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=omNxE4gsmXcdUOgEk6VOleDWGEBuxLgGbtiJkp3zxJrxK5F9vEQIP1rO+C9QmGuRvQMIoqLpMCo2Yi41IlvEdYKAyO3DVyvMizjX5GYNwHuupMfEDNVyPf/DFNTMXIbMM9jVfacplrtDujUpiS2p1BvfCdL8TVYmzexCAw663Lg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=gm67Tmfk; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="gm67Tmfk" ARC-Seal: i=1; a=rsa-sha256; t=1760129263; cv=none; d=zohomail.com; s=zohoarc; b=cOk65gf0X1V9g6/zByQrw6wOYqnTtYytkS1mjAHQcQmJVpBYZNBgVPoaslSvXFCYdsr2K1UsJAoCz+LNUYbcXS4OGwf+I+4Ot69ZP1/TBEgTyX9cKo89OOy/SRalT68nFFE8Ui6TWE+TAuyQjnCl1sjp7S5l4wOaQn99eLQo2bo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129263; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=zsTyD71EnFRPFV+ca+1K7KOHMBUKKghpyvfAY6H5pw4=; b=Y+G3b/pebbrph/GRYDEoqeQGL3CtNpqq31KM3kgNfm4AH4RVnwoHz6eujXEeuN00y6mgm+gnah4sGeop8hj+uOl/ZyUkggMwjFOH73WcZDFYYaDPdecp3oWvOJxCP5U8n8exXjC035DRU6GL0d0BNJ5TvvbC0q4vRXOX1Xwvj24= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129263; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=zsTyD71EnFRPFV+ca+1K7KOHMBUKKghpyvfAY6H5pw4=; b=gm67TmfknvarYMNvjIQqwMXpqoNT5KADTQOhCKHPvjmXkuffqX0KMihMiJtiz+xR jjHDGK7c6regGDveHehmVM39oPHFwDW9caUZInRCnd6YCvwUazmWtSnWGuzUjX4cqFO 9njs/D7ss27HK5dtPYlRtrpIAnXlahPi829cMf0U= Received: by mx.zohomail.com with SMTPS id 1760129261611721.6914981601944; Fri, 10 Oct 2025 13:47:41 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:09 +0200 Subject: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-1-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency. Add parent enables/disables where the recalc_rate op is called directly. Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enab= le (part 2)") Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enab= le (part 1)") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Nicolas Frattaroli Reviewed-by: Brian Masney --- drivers/clk/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 85d2f2481acf360f0618a4a382fb51250e9c2fc4..1b0f9d567f48e003497afc98df0= c0d2ad244eb90 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1921,7 +1921,14 @@ static unsigned long clk_recalc(struct clk_core *cor= e, unsigned long rate =3D parent_rate; =20 if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) { + if (core->flags & CLK_OPS_PARENT_ENABLE) + clk_core_prepare_enable(core->parent); + rate =3D core->ops->recalc_rate(core->hw, parent_rate); + + if (core->flags & CLK_OPS_PARENT_ENABLE) + clk_core_disable_unprepare(core->parent); + clk_pm_runtime_put(core); } return rate; @@ -4031,6 +4038,9 @@ static int __clk_core_init(struct clk_core *core) */ clk_core_update_duty_cycle_nolock(core); =20 + if (core->flags & CLK_OPS_PARENT_ENABLE) + clk_core_prepare_enable(core->parent); + /* * Set clk's rate. The preferred method is to use .recalc_rate. For * simple clocks and lazy developers the default fallback is to use the @@ -4046,6 +4056,9 @@ static int __clk_core_init(struct clk_core *core) rate =3D 0; core->rate =3D core->req_rate =3D rate; =20 + if (core->flags & CLK_OPS_PARENT_ENABLE) + clk_core_disable_unprepare(core->parent); + /* * Enable CLK_IS_CRITICAL clocks so newly added critical clocks * don't get accidentally disabled when walking the orphan tree and --=20 2.51.0 From nobody Fri Dec 19 12:16:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B804303A11; Fri, 10 Oct 2025 20:48:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129294; cv=pass; b=QrZHJr9gQhFao/H+MeqH1sHU8kS7EB3j+W4U4K5lDggeyzKd6TbUsaaUboICFug6kOD0vm127PwQ0cTzECG6KBq5uE8G4nHO/zLhnK8Srwl98iWJlOuovuyttctbkJPqaS3tXz+2WpeFYXxuNXif03OS7gpYQWfeDpU7GOqgrok= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129294; c=relaxed/simple; bh=8GUCaiNzqWDhN+ADy4rhGcVaSZLYP8oBvVrAvi+U7xc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WiHC7s3t7RIvzHyyxWB4PHbERc0MvCZXEA7uBaCFZl6xEZJ4rbEtNgcSp/DTLzl1v9F4vEITEL0TstRlUZOkb8147X1zhPVdk46oogKd5wBTEmEZfXJ67VyXwW34a8daXtcnJoNYCt6xCGM6au7Ps50OYn7Xkeu06R0t9sdsOQ8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=GN+O+O2e; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="GN+O+O2e" ARC-Seal: i=1; a=rsa-sha256; t=1760129267; cv=none; d=zohomail.com; s=zohoarc; b=eSCvhPR2NdeiDaGHNZX7X3W1uYCVXVHSnJGrjvj/xt4s3fukUm0aRNLb83FGUOA98Fpf+qgLVQeBJfe7QMG4GnDnMBlzCTVo8hMahtPZs06269uDtVC6J4qI8drj/+c33Qh4JcAHpBSeLDMkVYp3xTRP87pe/u4n9MEhWFfDYhA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129267; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=3++fXgIXc4/LRZtpwaII6fQKy3c0bv1cnXzTItgn82c=; b=h6C/VP+n1I5wUkWlJO9Ei2u8V1urt1RG8AR/XvZOKElze3yKg54GA1FnwkcjLcUzcWywcE5CEdVn8HIfJQ3qBWmJdhGQmF90SFulTkRkFk9KYHEz4zBzrZam22JNMaVNVBZeGMZmvXbe3KurhTin2ym7lYfEBb62YzuU2J9JglM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129267; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=3++fXgIXc4/LRZtpwaII6fQKy3c0bv1cnXzTItgn82c=; b=GN+O+O2eAWG38R0CHn3qKG+FWArOf7vCFCvWdmmPxhgjcfjvuXl7Q6gRD31p5+sz KGuFwiGCkZ4283vbndyx6gIo9PUDaq031Wtv8X3tokc6vq3hrjZbEZhSXadlk+ZFq8G 9JFB5WnL4VStc+07gCluTAJTwWaZm/5EZUNk1mIU= Received: by mx.zohomail.com with SMTPS id 1760129265113477.12854001630546; Fri, 10 Oct 2025 13:47:45 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:10 +0200 Subject: [PATCH v3 2/5] clk: mediatek: Refactor pll registration to pass device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-2-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stands, mtk_clk_register_plls takes a struct device_node pointer as its first argument. This is a tragic happenstance, as it's trivial to get the device_node from a struct device, but the opposite not so much. The struct device is a much more useful thing to have passed down. Refactor mtk_clk_register_plls to take a struct device pointer instead of a struct device_node pointer, and fix up all users of this function. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-mt2701.c | 2 +- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 4 ++-- drivers/clk/mediatek/clk-mt6765.c | 2 +- drivers/clk/mediatek/clk-mt6779.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt7629.c | 2 +- drivers/clk/mediatek/clk-mt7981-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt7988-apmixed.c | 2 +- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 3 ++- drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8196-mcu.c | 2 +- drivers/clk/mediatek/clk-mt8196-mfg.c | 2 +- drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 2 +- drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-pll.c | 7 ++++--- drivers/clk/mediatek/clk-pll.h | 10 ++++------ 24 files changed, 34 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 1e88ad8b93f4485ad40f842e19c68117e00a2fbe..d9f40fda73d1abc56ebc97ab755= bb48bd5f0991f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), + mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_div= s), clk_data); diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index a60622d251ff30fe8db2e596d87986a88f854e61..54b18e9f83f8f403460c77d8f5d= 4ea0737316774 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -119,7 +119,7 @@ static int clk_mt2712_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6735-apmixedsys.c index e0949911e8f7da7894b204012caefd0404cf8308..9e30c089a2092472bab889ede41= 9c41890c307a0 100644 --- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c @@ -93,8 +93,8 @@ static int clk_mt6735_apmixed_probe(struct platform_devic= e *pdev) return -ENOMEM; platform_set_drvdata(pdev, clk_data); =20 - ret =3D mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls, - ARRAY_SIZE(apmixedsys_plls), clk_data); + ret =3D mtk_clk_register_plls(&pdev->dev, apmixedsys_plls, + ARRAY_SIZE(apmixedsys_plls), clk_data); if (ret) { dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret); return ret; diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index d53731e7933f46d88ff180e43eb7163e52fb5b1c..60f6f9fa7dcf279631d0fa2eb30= a3bcbadef3225 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -740,7 +740,7 @@ static int clk_mt6765_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 86732f5acf93407a5aa99bc2f386f0728a06bb9b..4b9dcb910b03f1078212dc7089d= 7171d05de7e7f 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1220,7 +1220,7 @@ static int clk_mt6779_apmixed_probe(struct platform_d= evice *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index fb59e71af58e32d9419e036e3dbd28cdaa61cac3..ebf850ac57f540f2317e63dfabe= 94a953db3ae29 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -655,7 +655,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index 2350592d9a934f3ec8efb0cd8197e4c4fee49697..8a29eaab0cfcb7a389e09f8869b= 572d5886e2eaf 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -96,7 +96,7 @@ static int clk_mt7622_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index baf94e7bea373c59cb6333fdb483d00240b744c7..e154771b1b8bba7378af8a797c8= 1d0784b626e3b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -634,7 +634,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediat= ek/clk-mt7981-apmixed.c index e8211eb4e09e1a645f7e50a1e5814d29030c1757..6606b54fb376983ec7d49b00c2c= 0d1690c734058 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -76,7 +76,7 @@ static int clk_mt7981_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index 93751abe6be89784a102a0e5ac629d363ab3baaf..1c79418d08a77acf25cee914fb6= 573ac1707163e 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -74,7 +74,7 @@ static int clk_mt7986_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediat= ek/clk-mt7988-apmixed.c index 63d33a78cb48805f71aa6a74f8ed6b83f3b4fe22..416a4b88d100bb47bdb07e4f72b= c13208c8707a7 100644 --- a/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -86,7 +86,7 @@ static int clk_mt7988_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c index bdadc35c64cbd8987061c4442b8ff2f5fe50cc32..19e4ee489ec3905e92674ed0813= a9f60f9c28209 100644 --- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -57,7 +57,8 @@ static int clk_mt8135_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), + clk_data); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index adf576786696e0962dfd5147dfc8897bfaa48054..fb6c21bbeef81a383b56c8fada1= 799e0680676e5 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -105,7 +105,7 @@ static int clk_mt8167_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c index 551adbfd7ac9309bbc4f9beefe4f26230514f062..6242d4f5376e79346b2219b0a35= cf0c5ad755e49 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -155,7 +155,7 @@ static int clk_mt8183_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8188-apmixedsys.c index 21d7a9a2ab1af64cca6962960418d44c81dc664a..a1de596bff9945ca938504391e3= e33a4987d3a63 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -106,7 +106,7 @@ static int clk_mt8188_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index 8b45a3fad02f18df30e4c2ce2ba5b6338eae321f..a2d98ed58e34866b3d68bd0f85b= de339c258d822 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -66,7 +66,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_de= vice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), c= lk_data); + r =3D mtk_clk_register_plls(&pdev->dev, apusys_plls, + ARRAY_SIZE(apusys_plls), clk_data); if (r) goto free_apusys_pll_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8196-apmixedsys.c index 617f5449b88b8bcaf282e8ed8593b52413a233a8..c4ebb0170b82b979fbe7f03925f= 205325247d55d 100644 --- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c @@ -152,7 +152,8 @@ static int clk_mt8196_apmixed_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks, + clk_data); if (r) goto free_apmixed_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/c= lk-mt8196-mcu.c index 5cbcc411ae734c82b97bf099a645cb6aaa31d9c3..13642fc673c267a66027d1fa707= 3c9cfed68c682 100644 --- a/drivers/clk/mediatek/clk-mt8196-mcu.c +++ b/drivers/clk/mediatek/clk-mt8196-mcu.c @@ -122,7 +122,7 @@ static int clk_mt8196_mcu_probe(struct platform_device = *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, num_plls, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index ae1eb9de79ae2992b10a400c75e2e0324b100f66..8e09c0f7b7548f8e286671cea2d= ac64530b8ce47 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -105,7 +105,7 @@ static int clk_mt8196_mfg_probe(struct platform_device = *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, num_plls, clk_data); + r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c b/drivers/clk/media= tek/clk-mt8196-vlpckgen.c index d59a8a9d98550e897d18031d9bb814aa96d3cf57..7dcc164627c578ca93377425c3b= 21b46da4b4c28 100644 --- a/drivers/clk/mediatek/clk-mt8196-vlpckgen.c +++ b/drivers/clk/mediatek/clk-mt8196-vlpckgen.c @@ -664,7 +664,7 @@ static int clk_mt8196_vlp_probe(struct platform_device = *pdev) if (r) goto unregister_factors; =20 - r =3D mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls), + r =3D mtk_clk_register_plls(dev, vlp_plls, ARRAY_SIZE(vlp_plls), clk_data); if (r) goto unregister_muxes; diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c index f41b991a0178af3067b19a693512ec922af48e07..e331aa28a4bd58baf48a4aae160= 1cc80fc5661ac 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -133,7 +133,7 @@ static int clk_mt8365_apmixed_probe(struct platform_dev= ice *pdev) return PTR_ERR(hw); clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8516-apmixedsys.c index edd9174d2f2ff97a0c1198caa2a0b9c1ca40ffd2..2a6206cae2f087ff06fe60a6cf9= 6a0fa3143e567 100644 --- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -87,7 +87,7 @@ static int clk_mt8516_apmixed_probe(struct platform_devic= e *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index cd2b6ce551c6b0333cbe0a4f0d155ba2411f757a..5caf91ae9ddbe4f4d7052864adf= 0a5a70bda66bc 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include "clk-pll.h" @@ -404,7 +405,7 @@ void mtk_clk_unregister_pll(struct clk_hw *hw) kfree(pll); } =20 -int mtk_clk_register_plls(struct device_node *node, +int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data) { @@ -412,7 +413,7 @@ int mtk_clk_register_plls(struct device_node *node, int i; struct clk_hw *hw; =20 - base =3D of_iomap(node, 0); + base =3D of_iomap(dev->of_node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return -EINVAL; @@ -423,7 +424,7 @@ int mtk_clk_register_plls(struct device_node *node, =20 if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) { pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", - node, pll->id); + dev->of_node, pll->id); continue; } =20 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index d71c150ce83e4bb2fe78290c2d5570a90084246d..38fde1a273bff0a7a010a37356e= bc715fe0720d3 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -10,9 +10,7 @@ #include #include =20 -struct clk_ops; -struct clk_hw_onecell_data; -struct device_node; +struct device; =20 struct mtk_pll_div_table { u32 div; @@ -78,9 +76,9 @@ struct mtk_clk_pll { const struct mtk_pll_data *data; }; =20 -int mtk_clk_register_plls(struct device_node *node, - const struct mtk_pll_data *plls, int num_plls, - struct clk_hw_onecell_data *clk_data); +int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *p= lls, + int num_plls, struct clk_hw_onecell_data *clk_data); + void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, struct clk_hw_onecell_data *clk_data); =20 --=20 2.51.0 From nobody Fri Dec 19 12:16:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9231B302CC0; Fri, 10 Oct 2025 20:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129296; cv=pass; b=l/Z9MnqVM5uMh3ZqGE81HXPfA2M/JH2cgAbBKr6XkkYaaJJWHs1zTZCHbq7AYxf/MeeaeaVKZ0+oUwT3mrIGzEBGc9hcvdb2sYfBC5RjHcCDgybtHp39juiJEB/JfZKlIZ1p9KciRlyTaFLUyM3oKRyHnhFDzQkdXh/+KMAzFew= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129296; c=relaxed/simple; bh=W5UT/DGWxqLG+vJTxmNbFICyPcGXI9D0gQaAnXUTSF0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BlEbWgFfVGhPRc19LNvmMhH4vESESzng05bBdV4KUnNg6MKZQ017PN7iKhFGm1PResMNcUg3LjA0P5rnKmrK6f0ybERC8xKmYMSmQ2W0/S0VQQ8yl5Qg1sZCNXSdiKuimuPWCtuGdzbpTVpeNz1WSyXIvx/sqPEGgWZtA0yOkx8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=ArToftCJ; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="ArToftCJ" ARC-Seal: i=1; a=rsa-sha256; t=1760129269; cv=none; d=zohomail.com; s=zohoarc; b=Q6ekL3iEiAwGUU1vI++KUyIhWqYIBholVqOHIa1G10csdr79V2XRtG0R1wmdpEeTv3YCrUiZKMQdNrOe9Hp2rnqV50mcF4psJYnELvyY0eytS9rqUJPvDtdJbcYi7o7Nidv1D7UTyN5X9WlDU+/CJF7S6zt0uae1cpeNhlk+8J0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129269; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=32r8I0dbbvPxxnssyBIKBjZDYmfILScTBNW9LtvALP4=; b=dBg8bn3FHRe86YsOzhLvrNaMPMCZjyXRF8OdEKAPR1c/52z1YZs+P5iiBH9yKwT0AE7nnOsLG/V1WUMJ38OnV40BqujluuSvwJwKVGUt/c0Cx5UVh4ybGNl2itVsN724S/qENbwr/uoW7I//HwC/o+JSo6FMFv0+4LCfcAOliZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129269; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=32r8I0dbbvPxxnssyBIKBjZDYmfILScTBNW9LtvALP4=; b=ArToftCJpNVDosIkvFQTfMdG0tY2Aw/N3t+/kfTATAh7x1ExI9K8Zr5LzOg9t3bZ ebOH/+cTYNQRBV6+YswWIiu0yhJUMC5sw3YaESF7IvDYl4FH4owXWo3Hb3j0jVmapog 5AQrgWxUcNaMfz+UhG04oOX+QRdTUoQTgSGUOw14= Received: by mx.zohomail.com with SMTPS id 176012926846849.15724721205868; Fri, 10 Oct 2025 13:47:48 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:11 +0200 Subject: [PATCH v3 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-3-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Passing the struct device pointer to clk_hw_register allows for runtime power management to work for the registered clock controllers. However, the mediatek PLL clocks do not do this. Change this by adding a struct device pointer argument to mtk_clk_register_pll, and fix up the only other user of it. Also add a new member to the struct mtk_clk_pll for the struct device pointer, which is set by mtk_clk_register_pll and is used by mtk_clk_register_pll_ops. If mtk_clk_register_pll is called with a NULL struct device pointer, then everything still works as expected; the clock core will simply treat them as previously, i.e. without runtime power management. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-pll.c | 9 ++++++--- drivers/clk/mediatek/clk-pll.h | 4 +++- drivers/clk/mediatek/clk-pllfh.c | 2 +- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 5caf91ae9ddbe4f4d7052864adf0a5a70bda66bc..c4f9c06e5133dbc5902f261353c= 197fbde95e54d 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -366,7 +366,7 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, init.parent_names =3D &parent_name; init.num_parents =3D 1; =20 - ret =3D clk_hw_register(NULL, &pll->hw); + ret =3D clk_hw_register(pll->dev, &pll->hw); =20 if (ret) return ERR_PTR(ret); @@ -374,7 +374,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, return &pll->hw; } =20 -struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, +struct clk_hw *mtk_clk_register_pll(struct device *dev, + const struct mtk_pll_data *data, void __iomem *base) { struct mtk_clk_pll *pll; @@ -385,6 +386,8 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pl= l_data *data, if (!pll) return ERR_PTR(-ENOMEM); =20 + pll->dev =3D dev; + hw =3D mtk_clk_register_pll_ops(pll, data, base, pll_ops); if (IS_ERR(hw)) kfree(pll); @@ -428,7 +431,7 @@ int mtk_clk_register_plls(struct device *dev, continue; } =20 - hw =3D mtk_clk_register_pll(pll, base); + hw =3D mtk_clk_register_pll(dev, pll, base); =20 if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", pll->name, diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index 38fde1a273bff0a7a010a37356ebc715fe0720d3..f6493699c4e367b45038ceede95= 65ae42a030b47 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -61,6 +61,7 @@ struct mtk_pll_data { */ =20 struct mtk_clk_pll { + struct device *dev; struct clk_hw hw; void __iomem *base_addr; void __iomem *pd_addr; @@ -108,7 +109,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, const struct mtk_pll_data *data, void __iomem *base, const struct clk_ops *pll_ops); -struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data, +struct clk_hw *mtk_clk_register_pll(struct device *dev, + const struct mtk_pll_data *data, void __iomem *base); void mtk_clk_unregister_pll(struct clk_hw *hw); =20 diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index 83630ee07ee976bf980c8cf2dd35ea24c1b40821..62bfe4a480f14a0a742fb094aff= 0e6d1a79fe0c3 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -220,7 +220,7 @@ int mtk_clk_register_pllfhs(struct device_node *node, if (use_fhctl) hw =3D mtk_clk_register_pllfh(pll, pllfh, base); else - hw =3D mtk_clk_register_pll(pll, base); + hw =3D mtk_clk_register_pll(NULL, pll, base); =20 if (IS_ERR(hw)) { pr_err("Failed to register %s clk %s: %ld\n", --=20 2.51.0 From nobody Fri Dec 19 12:16:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 573B0303A26; Fri, 10 Oct 2025 20:48:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129297; cv=pass; b=cNuYF9WoYE6Mc0bTKZNP7kd+Ozg6UhAS/+8RgieRj8v6mvscUAAfACckVVblSd15FhKuNSzySDtHCZTVJUKAbtVqUn0W2A5h1yqmgt5YdewcWqW7NHII74VyhtUnAOvPtZlgr8OpOx1YXtnGWXeoP0qaWaFI18+RdMe5eZETXc4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129297; c=relaxed/simple; bh=92D6FZZC301x+KfnnCs1GRBKU+67f3TXVmiREp0Oet8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dr3eCBGVxf26bvzbh5D0RlRtkdDWAxs4F3JTjDhHPwfULEHcFk6+DKjYMab/E0WQb5e0x56cgB+IwC+hTwJWuFYpabR91zG2i1IjzXBDZN7An3LwLmJdZ1xM8zksQMRoPeIS7RqVjE/fhkDBEvLAl5DMqBKlHG5wBPWGr63X6LE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=KQbO5wPZ; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="KQbO5wPZ" ARC-Seal: i=1; a=rsa-sha256; t=1760129273; cv=none; d=zohomail.com; s=zohoarc; b=brEp0Mv54PwELGVXmK3qAZdMbKPPmHXS0F6u3wRbU/IUv78MHDySmS0RzLQGDPruByi/B42EzpIYrpy5J5sCuaCdheznGIiq3AIPPos0dnIKWjzEjoXyOGiSmJzrkz245UIDDEOaEQvNrQ7PEr5CmdlPnkfg0sDzPtnlQS6Df/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129273; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=dvR0nVJz3qP3rSUx5baNKuQSFe2J2wvzDrszjuc2XJQ=; b=GijkgAeINz41ZvWtLhmS1qt7xKiwxJdd8wfmknHN7Pwdn6mYfLwVXrgCb3A5CmKCQllVvUR+e8mtVEataeYSvA368usheonDgavRxUX4bFNUTw2pbMBksorUhFEjNK/7+RessGic+cUpjI8Lo2RcsnGXHUThJfHtbgTGg3RUrYA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129273; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=dvR0nVJz3qP3rSUx5baNKuQSFe2J2wvzDrszjuc2XJQ=; b=KQbO5wPZoZQjCai/RUmLCV3w9+rIfIRunMdCm+2MGYj88qKuKuQArk+WkfM3Wt87 Dp+XCQapXuIMvNIBEPk7lM2EsdhT7y62ZQneZMT52D1QYmdbyRfclfCl0am8sQ2KzhM PJ1lKakhLKLB+ganhXtKXwuhl4vgQaPSSmQnlcWU= Received: by mx.zohomail.com with SMTPS id 1760129271811594.0370826679009; Fri, 10 Oct 2025 13:47:51 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:12 +0200 Subject: [PATCH v3 4/5] clk: mediatek: Refactor pllfh registration to pass device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-4-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 After refactoring all of PLL to pass the device, it's now fairly easy to refactor pllfh and its users, as pllfh registration wraps PLL registration. Do this refactor and move all of the pllfh users to pass the device as well. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++------- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-pllfh.c | 13 ++++++++----- drivers/clk/mediatek/clk-pllfh.h | 2 +- 7 files changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 91665d7f125efde4941cc4de881c5b503a935529..123d5d7fea8554676364dc56f5c= 023e43325d516 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -152,7 +152,7 @@ static int clk_mt6795_apmixed_probe(struct platform_dev= ice *pdev) return -ENOMEM; =20 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - ret =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + ret =3D mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index 95385bb67d5511eda3a851f81986e67eaf81e5fb..d7d416172ab35bc027ae67c163c= 1dc20dee857b6 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -140,13 +140,13 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed); static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { const u8 *fhctl_node =3D "mediatek,mt8173-fhctl"; - struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; + struct device *dev =3D &pdev->dev; void __iomem *base; struct clk_hw *hw; int r; =20 - base =3D of_iomap(node, 0); + base =3D of_iomap(dev->of_node, 0); if (!base) return -ENOMEM; =20 @@ -157,25 +157,25 @@ static int clk_mt8173_apmixed_probe(struct platform_d= evice *pdev) } =20 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), - pllfhs, ARRAY_SIZE(pllfhs), clk_data); + r =3D mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; =20 hw =3D mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_= REF2USB); if (IS_ERR(hw)) { r =3D PTR_ERR(hw); - dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); + dev_err(dev, "Failed to register ref2usb_tx: %d\n", r); goto unregister_plls; } clk_data->hws[CLK_APMIXED_REF2USB_TX] =3D hw; =20 - hw =3D devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m"= , 0, + hw =3D devm_clk_hw_register_divider(dev, "hdmi_ref", "tvdpll_594m", 0, base + REGOFF_HDMI_REF, 16, 3, CLK_DIVIDER_POWER_OF_TWO, NULL); clk_data->hws[CLK_APMIXED_HDMI_REF] =3D hw; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_dat= a); if (r) goto unregister_ref2usb; =20 diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index 4b2b16578232d986f78deed4778c5fab7f460184..d35dd2632e43ab535b32b8b99f8= d75de02d56fe2 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -151,7 +151,7 @@ static int clk_mt8186_apmixed_probe(struct platform_dev= ice *pdev) =20 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); =20 - r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c index 0b66a27e4d5ac68f09dc6a4197fd84ef82342df9..b0563a285bd666d492a7fa94073= 3aad1ab1a0bae 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -162,7 +162,7 @@ static int clk_mt8192_apmixed_probe(struct platform_dev= ice *pdev) =20 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); =20 - r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 282a3137dc89419a6d0b574fd549cee941687900..44917ab034c56f01ef02d1957f1= 7eb0655438d75 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -181,7 +181,7 @@ static int clk_mt8195_apmixed_probe(struct platform_dev= ice *pdev) =20 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); =20 - r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index 62bfe4a480f14a0a742fb094aff0e6d1a79fe0c3..8ad11023d91127e88900bc6bcab= baeafb1e00664 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include "clk-mtk.h" #include "clk-pllfh.h" @@ -149,7 +150,7 @@ static bool fhctl_is_supported_and_enabled(const struct= mtk_pllfh_data *pllfh) } =20 static struct clk_hw * -mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data, +mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_= data, struct mtk_pllfh_data *pllfh_data, void __iomem *base) { struct clk_hw *hw; @@ -166,6 +167,8 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_d= ata, goto out; } =20 + fh->clk_pll.dev =3D dev; + hw =3D mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, &mtk_pllfh_ops); =20 @@ -194,7 +197,7 @@ static void mtk_clk_unregister_pllfh(struct clk_hw *hw) kfree(fh); } =20 -int mtk_clk_register_pllfhs(struct device_node *node, +int mtk_clk_register_pllfhs(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_fhs, struct clk_hw_onecell_data *clk_data) @@ -203,7 +206,7 @@ int mtk_clk_register_pllfhs(struct device_node *node, int i; struct clk_hw *hw; =20 - base =3D of_iomap(node, 0); + base =3D of_iomap(dev->of_node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return -EINVAL; @@ -218,9 +221,9 @@ int mtk_clk_register_pllfhs(struct device_node *node, use_fhctl =3D fhctl_is_supported_and_enabled(pllfh); =20 if (use_fhctl) - hw =3D mtk_clk_register_pllfh(pll, pllfh, base); + hw =3D mtk_clk_register_pllfh(dev, pll, pllfh, base); else - hw =3D mtk_clk_register_pll(NULL, pll, base); + hw =3D mtk_clk_register_pll(dev, pll, base); =20 if (IS_ERR(hw)) { pr_err("Failed to register %s clk %s: %ld\n", diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pl= lfh.h index 5f419c2ec01f988ede4e40289c6e5d5f8070ad14..a4f337acad71389f77118790888= 2b09d0f801868 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -68,7 +68,7 @@ struct fh_operation { int (*ssc_enable)(struct mtk_fh *fh, u32 rate); }; =20 -int mtk_clk_register_pllfhs(struct device_node *node, +int mtk_clk_register_pllfhs(struct device *dev, const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_pllfhs, struct clk_hw_onecell_data *clk_data); --=20 2.51.0 From nobody Fri Dec 19 12:16:01 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97D2A303CAA; Fri, 10 Oct 2025 20:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129301; cv=pass; b=TD4c1Okg3GbMzllRnGzwyarewGO+DBFq82jy8+yqjuJi3rG5w2EExZy9vzvd5BxDwIBokUi7vq6ltkHT8jXbblUsid9uoftAS9POR/x2pbOBHH0BisyV5HJ0kMQqNBjQL6MObTI59ZDXze5BGfmlp2EoY9DqlL6XdnErita4l0c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760129301; c=relaxed/simple; bh=DqdxqtZA+JTQXfSgoa0iFFT+t9Xu2GNK7V17jWtmqQQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JPq3bXmHihrGdTWoMBy51LVlP+fcXA/GkYSQrC20eb1nrrHlp+GD8cyrs0ksteFn2qfJQQUrIGuLSTb/tRZz7/CTXVgl3hTI8foqvLklntThogPuTGK75r5OgkhKaEx1nyhwFJDoUn/EXmC11MmjsvkC7eGCO9wiTwG9hcWfq5s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=QQFrYdfr; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="QQFrYdfr" ARC-Seal: i=1; a=rsa-sha256; t=1760129277; cv=none; d=zohomail.com; s=zohoarc; b=FRB1JV3sOZSZ9JTFNpfXOd2Bv8HgJlwn+Mwuqs0hNoS0vUgHnNLQABUEEvKPwxcqs3HP2vmQ3oQMjStn/fgxJRPyISByAOhp0A9TUlyDa/TrDgVilXzXGq+intdCBoZ3w57VhUXsOh1XOFsBzEc53ExgQcY0v0xuAc+R2Mrpcz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760129277; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=bZycTGcqflUTi8jckNmrkgc5LMZTQ/XWz04YrmhHY6Q=; b=lPEXIiqFJRpWR/7jKD5QtjKQUs4Ld6oAxVW7o3FszBl6VucePAMws4ilY0NR9aifc6ohf+PoaBfg3CzSMl/Qn9G+oTxjoRC6PfQOWb7K+1sipM2PS95sX/fZWFFhXfvdOblKxw4aTR8ly/xPgyY5/w3O6DXA4nBzQ7nvA2RTGEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760129277; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=bZycTGcqflUTi8jckNmrkgc5LMZTQ/XWz04YrmhHY6Q=; b=QQFrYdfrOeZ1cCsQWfyZDKWD1n7ctc7DQvvMPQyevQLJBwGe9xZFN4Vs+bXqE/5/ fZO2UAwhibKoElCFigRrflEaoUKfPSpInZ21hGxZah1FYWs9YS3c9HmqH7lYJ/ZczqU lQt3qv7b6VjE6k/GklM2bYNOZ5AsuHzZp83XWW3A= Received: by mx.zohomail.com with SMTPS id 1760129275139615.3748636428318; Fri, 10 Oct 2025 13:47:55 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 10 Oct 2025 22:47:13 +0200 Subject: [PATCH v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251010-mtk-pll-rpm-v3-5-fb1bd15d734a@collabora.com> References: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> In-Reply-To: <20251010-mtk-pll-rpm-v3-0-fb1bd15d734a@collabora.com> To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Dong Aisheng , Matthias Brugger , Yassine Oudjana , Laura Nao , =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 All the MFGPLL require MFG_EB to be on for any operation on them, and they only tick when MFG_EB is on as well, therefore making this a parent-child relationship. This dependency wasn't clear during the initial upstreaming of these clock controllers, as it only made itself known when I could observe the effects of the clock by bringing up a different piece of hardware. Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it when initialising the pll to then translate it into the actual CLK_OPS_PARENT_ENABLE flag. Then add the mfg_eb parent to the mfgpll clocks, and set the new PLL_PARENT_EN flag. Fixes: 03dc02f8c7dc ("clk: mediatek: Add MT8196 mfg clock support") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/clk/mediatek/clk-mt8196-mfg.c | 13 +++++++------ drivers/clk/mediatek/clk-pll.c | 3 +++ drivers/clk/mediatek/clk-pll.h | 1 + 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index 8e09c0f7b7548f8e286671cea2dac64530b8ce47..a317183f1681bc6e8167c44b2bb= e4a78566ba639 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -58,24 +58,25 @@ .pcw_shift =3D _pcw_shift, \ .pcwbits =3D _pcwbits, \ .pcwibits =3D MT8196_INTEGER_BITS, \ + .parent_name =3D "mfg_eb", \ } =20 static const struct mtk_pll_data mfg_ao_plls[] =3D { - PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0, - BIT(0), MFGPLL_CON1, 24, 0, 0, 0, + PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, + PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22), }; =20 static const struct mtk_pll_data mfgsc0_ao_plls[] =3D { PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, - MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0, - MFGPLL_SC0_CON1, 0, 22), + MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24, + 0, 0, 0, MFGPLL_SC0_CON1, 0, 22), }; =20 static const struct mtk_pll_data mfgsc1_ao_plls[] =3D { PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, - MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0, - MFGPLL_SC1_CON1, 0, 22), + MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24, + 0, 0, 0, MFGPLL_SC1_CON1, 0, 22), }; =20 static const struct of_device_id of_match_clk_mt8196_mfg[] =3D { diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index c4f9c06e5133dbc5902f261353c197fbde95e54d..0f3759fcd9d0228c23f4916d041= d17b731a6c838 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -359,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_= pll *pll, =20 init.name =3D data->name; init.flags =3D (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; + if (data->flags & PLL_PARENT_EN) + init.flags |=3D CLK_OPS_PARENT_ENABLE; + init.ops =3D pll_ops; if (data->parent_name) init.parent_names =3D &data->parent_name; diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f6493699c4e367b45038ceede9565ae42a030b47..f49dc2732ffee50ebf023c01b51= 3d74989a6ec7b 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -19,6 +19,7 @@ struct mtk_pll_div_table { =20 #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) +#define PLL_PARENT_EN BIT(2) #define POSTDIV_MASK GENMASK(2, 0) =20 struct mtk_pll_data { --=20 2.51.0