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[144.49.247.19]) by smtp-relay.gmail.com with ESMTPS id 586e51a60fabf-3c8c8f0679asm54199fac.19.2025.10.09.14.20.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Oct 2025 14:20:40 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-85a0492b5feso729320585a.0 for ; Thu, 09 Oct 2025 14:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1760044839; x=1760649639; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UNu9C7+Hl8/zwgHRFvABJRp0xk1fvGWapoEQB/t9/po=; b=d+kR+mElxGy8bGEzQ2CrkO4Bwv1h9Anq9WIYjKsOPs+LtDErI9BLTjaVDma0g0j7qz wa7Aufn1mfaebpWhEuK33/yvEZzjgeKg4VFpl/qQ0F29mc9ukZameBX5eBa8jJnVodk8 HkHIOGUNCsBqc4UIrRPGDQy6nzcXi8j5y4I/w= X-Forwarded-Encrypted: i=1; AJvYcCUjRbSPor5gpXe0xfgGqpyXlruz+5AyUrdLWVZLiy2siWt7YcDGeHDb77DD3Q0bI3yfAqwWq9pycoC206k=@vger.kernel.org X-Received: by 2002:a05:620a:d89:b0:86a:3188:bb49 with SMTP id af79cd13be357-883525c06f8mr1579828885a.54.1760044839302; Thu, 09 Oct 2025 14:20:39 -0700 (PDT) X-Received: by 2002:a05:620a:d89:b0:86a:3188:bb49 with SMTP id af79cd13be357-883525c06f8mr1579823385a.54.1760044838777; Thu, 09 Oct 2025 14:20:38 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8849f9ae428sm274832685a.16.2025.10.09.14.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Oct 2025 14:20:38 -0700 (PDT) From: Kamal Dasu To: peng.fan@oss.nxp.com, andersson@kernel.org, baolin.wang@linux.alibaba.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com Cc: bcm-kernel-feedback-list@broadcom.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kamal Dasu Subject: [PATCH v3 2/3] hwspinlock: brcmstb hardware semaphore support Date: Thu, 9 Oct 2025 17:20:02 -0400 Message-Id: <20251009212003.2714447-3-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251009212003.2714447-1-kamal.dasu@broadcom.com> References: <20251009212003.2714447-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Broadcom settop SoCs have common 16 hardware semaphore registers that can be used as part of the kernel hardware spinlock framework. The hardware semaphores are part of the 'sundry' ip block that also has controls like pin/mux controls, SoC identification, drive strength, reset controls, and other misc bits. Adding support for brmstb_hwspinlock that only maps sundry block registers SUN_TOP_CTRL_SEMAPHORE_[0:15] to implement the hardware spinlock operations. Change allows other Broadcom settop drivers to call hwspin_trylock() and hwspin_unlock() interfaces to make use of hwspinlock framework. Other driver dt nodes just need to provide a reference to the &hwspinlock and lock id to make use of a particular hardware lock. e.g. hwlocks =3D <&hwspinlock0 0>; Signed-off-by: Kamal Dasu --- drivers/hwspinlock/Kconfig | 11 ++- drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/brcmstb_hwspinlock.c | 96 +++++++++++++++++++++++++ 3 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 drivers/hwspinlock/brcmstb_hwspinlock.c diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index 3874d15b0e9b..39797cadfd0b 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -8,6 +8,16 @@ menuconfig HWSPINLOCK =20 if HWSPINLOCK =20 +config HWSPINLOCK_BRCMSTB + tristate "Broadcom Setttop Hardware Semaphore functionality" + depends on ARCH_BRCMSTB || COMPILE_TEST + help + Broadcom settop hwspinlock driver. + Say y here to support the Broadcom Hardware Semaphore functionality, wh= ich + provides a synchronisation mechanism on the SoC. + + If unsure, say N. + config HWSPINLOCK_OMAP tristate "OMAP Hardware Spinlock device" depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX || SOC_AM4= 3XX || ARCH_K3 || COMPILE_TEST @@ -62,5 +72,4 @@ config HSEM_U8500 SoC. =20 If unsure, say N. - endif # HWSPINLOCK diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index a0f16c9aaa82..35f2d94d8ba2 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -4,6 +4,7 @@ # =20 obj-$(CONFIG_HWSPINLOCK) +=3D hwspinlock_core.o +obj-$(CONFIG_HWSPINLOCK_BRCMSTB) +=3D brcmstb_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_OMAP) +=3D omap_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_QCOM) +=3D qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SPRD) +=3D sprd_hwspinlock.o diff --git a/drivers/hwspinlock/brcmstb_hwspinlock.c b/drivers/hwspinlock/b= rcmstb_hwspinlock.c new file mode 100644 index 000000000000..0b164c57192e --- /dev/null +++ b/drivers/hwspinlock/brcmstb_hwspinlock.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * brcmstb HWSEM driver + * + * Copyright (C) 2025 Broadcom + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "hwspinlock_internal.h" + +#define BRCMSTB_NUM_SEMAPHORES 16 +#define RESET_SEMAPHORE 0 + +#define HWSPINLOCK_VAL 'L' + +static int brcmstb_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr =3D (void __iomem *)lock->priv; + + writel(HWSPINLOCK_VAL, lock_addr); + + return (readl(lock_addr) =3D=3D HWSPINLOCK_VAL); +} + +static void brcmstb_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr =3D (void __iomem *)lock->priv; + + /* release the lock by writing 0 to it */ + writel(RESET_SEMAPHORE, lock_addr); +} + +static void brcmstb_hwspinlock_relax(struct hwspinlock *lock) +{ + ndelay(50); +} + +static const struct hwspinlock_ops brcmstb_hwspinlock_ops =3D { + .trylock =3D brcmstb_hwspinlock_trylock, + .unlock =3D brcmstb_hwspinlock_unlock, + .relax =3D brcmstb_hwspinlock_relax, +}; + +static int brcmstb_hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_device *bank; + struct hwspinlock *hwlock; + void __iomem *io_base; + int i, num_locks =3D BRCMSTB_NUM_SEMAPHORES; + + io_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(io_base)) { + dev_err(&pdev->dev, "semaphore iobase mapping error\n"); + return PTR_ERR(io_base); + } + + bank =3D devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), + GFP_KERNEL); + if (!bank) + return -ENOMEM; + + for (i =3D 0, hwlock =3D &bank->lock[0]; i < num_locks; i++, hwlock++) + hwlock->priv =3D (void __iomem *)(io_base + sizeof(u32) * i); + + return devm_hwspin_lock_register(&pdev->dev, bank, + &brcmstb_hwspinlock_ops, + 0, num_locks); +} + +static const struct of_device_id brcmstb_hwspinlock_ids[] =3D { + { .compatible =3D "brcm,brcmstb-hwspinlock", }, + { /* end */ }, +}; +MODULE_DEVICE_TABLE(of, brcmstb_hwspinlock_ids); + +static struct platform_driver brcmstb_hwspinlock_driver =3D { + .probe =3D brcmstb_hwspinlock_probe, + .driver =3D { + .name =3D "brcmstb_hwspinlock", + .of_match_table =3D brcmstb_hwspinlock_ids, + }, +}; + +module_platform_driver(brcmstb_hwspinlock_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Hardware Spinlock driver for brcmstb"); +MODULE_AUTHOR("Kamal Dasu "); --=20 2.34.1