From nobody Mon Feb 9 19:55:37 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D672B29405 for ; Thu, 9 Oct 2025 13:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760017456; cv=none; b=K6u3asLGsrLFxJKUhILY7ExRe/fM9IIjHxVk+maE2/krMPqEK4AEtXrrEGwbfNNUFlougrlO5UUIYyB5kWO/XCnUTyxk/t/gxn1qhcJgyYe9Bw5ZnGod73nqbEvbjn9qp6sw99df7gPYyDIxwulYx2kHxeT8KJLJ+ZMHx7a52XE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760017456; c=relaxed/simple; bh=dChHmzheAUOopLiMjsUNyL3WKZIZYn48m0bZ4AM75UM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u/p3ViqZ+vfodsFKi7b10QXsfYb4JbZIVZzjs6vRcXroD+97BgEp9d/+eeynkCwaMJwLvNZRTPV4xm7UD8yyJBZ6Os278CO3jcto6wJSTZFqO1KRrgYRBIcyaXWLiz5JGZLBJYAB1gVK5455/Wd9Yr2PXASFgfWmhPJPa0FkWGQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from Mobilestation.localdomain (unknown [183.6.60.79]) by APP-01 (Coremail) with SMTP id qwCowACX76EEvOdoFFc_DQ--.1956S3; Thu, 09 Oct 2025 21:43:47 +0800 (CST) From: Yao Zihong To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ajones@ventanamicro.com, alexghiti@rivosinc.com, shuah@kernel.org, samuel.holland@sifive.com, evan@rivosinc.com, cleger@rivosinc.com, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, zhangyin2018@iscas.ac.cn, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Charlie Jenkins , Cyan Yang , Yunhui Cui , Aleksa Paunovic , Jesse Taube , Inochi Amaoto Subject: [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key Date: Thu, 9 Oct 2025 21:41:51 +0800 Message-ID: <20251009134318.23040-2-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> References: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowACX76EEvOdoFFc_DQ--.1956S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Ww4DAw1rXr15tr4rCw1Utrb_yoW8Cr1xpF 4Durs5WFZ0kr4xCayxt3Wv9w1kJwnxKw45tw1Uu3yUXa47tw4rXrWDta9FkF1DtFWFqayI gF4agrWvqa9FyrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQ0b7Iv0xC_tr1lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r1j6r4UM28EF7xvwVC2z280aVCY 1x0267AKxVW8JVW8Jr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I 8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCF s4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFI xGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l 4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67 AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8I cVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI 8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v2 6r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTR2g4hUUUUU X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE to expose the block size (in bytes) when Zicbop is supported. Signed-off-by: Yao Zihong Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 948d2b34e94e..2f278c395af9 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 14 +#define RISCV_HWPROBE_MAX_KEY 15 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 5d30a4fae37a..9cc508be54c5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -82,6 +82,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56) #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57) #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58) +#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 59) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -107,6 +108,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14 +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ --=20 2.47.2 From nobody Mon Feb 9 19:55:37 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4752D29405 for ; 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dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from Mobilestation.localdomain (unknown [183.6.60.79]) by APP-01 (Coremail) with SMTP id qwCowACX76EEvOdoFFc_DQ--.1956S4; Thu, 09 Oct 2025 21:43:56 +0800 (CST) From: Yao Zihong To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ajones@ventanamicro.com, alexghiti@rivosinc.com, shuah@kernel.org, samuel.holland@sifive.com, evan@rivosinc.com, cleger@rivosinc.com, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, zhangyin2018@iscas.ac.cn, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Charlie Jenkins , Jesse Taube , Inochi Amaoto , Aleksa Paunovic , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Yunhui Cui , Nam Cao Subject: [PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size Date: Thu, 9 Oct 2025 21:41:52 +0800 Message-ID: <20251009134318.23040-3-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> References: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowACX76EEvOdoFFc_DQ--.1956S4 X-Coremail-Antispam: 1UD129KBjvdXoWruF4DZFW5Aw13KF17Cw4kJFb_yoWkZwc_uw 17Jas8u34UCFW09FWvyw4FkwsIyw4kJa48Ar1ftr1DZF1UAryUXas8Ca47Ww1DZw1DXasx CrWrW39rZ3W2vjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbkkFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUXwA2048vs2IY02 0Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1l84 ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0x vEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVj vjDU0xZFpf9x0pRHKZLUUUUU= X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Plumb Zicbop into hwprobe. Semantics mirror Zicbom/Zicboz to keep userspace expectations aligned. Signed-off-by: Yao Zihong Reviewed-by: Andrew Jones --- arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 000f4451a9d8..7a6ae1327504 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCB); EXT_KEY(ZCMOP); EXT_KEY(ZICBOM); + EXT_KEY(ZICBOP); EXT_KEY(ZICBOZ); EXT_KEY(ZICNTR); EXT_KEY(ZICOND); @@ -293,6 +294,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM)) pair->value =3D riscv_cbom_block_size; break; + case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE: + pair->value =3D 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP)) + pair->value =3D riscv_cbop_block_size; + break; case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS: pair->value =3D user_max_virt_addr(); break; --=20 2.47.2 From nobody Mon Feb 9 19:55:37 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 769402E8B74; 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charset="utf-8" Update hwprobe.rst to include documentation of the new :c:macro:`RISCV_HWPROBE_EXT_ZICBOP` and :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`, following the same style as the Zicbom and Zicboz entries. The extension bit records support for the Zicbop extension, and the block size key reports the block size in bytes. Signed-off-by: Yao Zihong --- Documentation/arch/riscv/hwprobe.rst | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2f449c9b15bd..3b9c9d7e1409 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -275,6 +275,9 @@ The following keys are defined: ratified in commit 49f49c842ff9 ("Update to Rafified state") of riscv-zabha. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported= , as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar val= ues to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. @@ -369,4 +372,7 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq vendor extension is supported in version 1.0 of Matrix Multiply Ac= cumulate - Instruction Extensions Specification. \ No newline at end of file + Instruction Extensions Specification. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicbop block in bytes. \ No newline at end of file --=20 2.47.2 From nobody Mon Feb 9 19:55:37 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A6362E8E1F; Thu, 9 Oct 2025 13:44:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760017479; cv=none; b=Da+3OCcKUBAcCPLO8ucJhJ010U+oJR1BdJ77mottWjqkgrYtJUi4yMNI7PpSeunQi7FiHq91f589/orz5OqfLhN2Sgm0bBmGZcxEtMrV0ZWCzewpKIxSZ1ujir70A+utC2qumGNToCommLSvtzVqMP47qaSNusF81HNg2F2EnGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760017479; c=relaxed/simple; bh=xpyO27wStAAmGxSSMjaSNXERYYHjXfNJ7MohxZUHNU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eY3Oi7OUj7wv9AVYU3BlvIBZPeonEF66URSXWMMX3GqUyfSuWYEHqDKGJMFjld4UQtYlASagFCCKaKutGi8uN9CjJb28E6GXmVX3ooFT9ukfO87Z1JAtXQkCGIZvrZFx6ML56OYTZl9LtGHX+njzUQMnRO4Xvasb9yySD5ilkzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from Mobilestation.localdomain (unknown [183.6.60.79]) by APP-01 (Coremail) with SMTP id qwCowACX76EEvOdoFFc_DQ--.1956S6; Thu, 09 Oct 2025 21:44:23 +0800 (CST) From: Yao Zihong To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ajones@ventanamicro.com, alexghiti@rivosinc.com, shuah@kernel.org, samuel.holland@sifive.com, evan@rivosinc.com, cleger@rivosinc.com, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, zhangyin2018@iscas.ac.cn, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST FRAMEWORK) Subject: [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test Date: Thu, 9 Oct 2025 21:41:54 +0800 Message-ID: <20251009134318.23040-5-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> References: <20251009134318.23040-1-zihong.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowACX76EEvOdoFFc_DQ--.1956S6 X-Coremail-Antispam: 1UD129KBjvJXoW3JFWkGw43AF48uw17CFyDWrg_yoW3WFyfpa 95ur4YqF48AF47KayxJF4DGFsYgr1vq3yUArWru3s8Z347Xas3JF97Ka9rAFWkGry8Zry5 uF13tFWruFW7JaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4U JwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2 kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCY1x0264kExVAvwVAq07x20xyl42xK82IYc2Ij 64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY 1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUUMKZtUUUUU== X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Add a new selftest under hwprobe/ to verify Zicbop extension behavior. The test checks: - That hwprobe correctly reports Zicbop presence and block size. - That prefetch instructions execute without exception on valid and NULL addresses when Zicbop is present. - That prefetch.{i,r,w} do not trigger SIGILL even when Zicbop is absent, since Zicbop instructions are defined as hints. The test is based on cbo.c but adapted for Zicbop prefetch instructions. Signed-off-by: Yao Zihong --- .../testing/selftests/riscv/hwprobe/Makefile | 5 +- .../selftests/riscv/hwprobe/prefetch.c | 236 ++++++++++++++++++ 2 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing= /selftests/riscv/hwprobe/Makefile index cec81610a5f2..3c8b8ba7629c 100644 --- a/tools/testing/selftests/riscv/hwprobe/Makefile +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -4,7 +4,7 @@ =20 CFLAGS +=3D -I$(top_srcdir)/tools/include =20 -TEST_GEN_PROGS :=3D hwprobe cbo which-cpus +TEST_GEN_PROGS :=3D hwprobe cbo which-cpus prefetch =20 include ../../lib.mk =20 @@ -16,3 +16,6 @@ $(OUTPUT)/cbo: cbo.c sys_hwprobe.S =20 $(OUTPUT)/which-cpus: which-cpus.c sys_hwprobe.S $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/prefetch: prefetch.c sys_hwprobe.S + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/hwprobe/prefetch.c b/tools/testi= ng/selftests/riscv/hwprobe/prefetch.c new file mode 100644 index 000000000000..d9ea048325fb --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/prefetch.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Ventana Micro Systems Inc. + * Copyright (c) 2025 PLCT Lab, ISCAS + * + * Based on tools/testing/selftests/riscv/hwprobe/cbo.c with modifications + * for Zicbop prefetch testing. + * + * Run with 'taskset -c prefetch' to only execute hwprobe on a + * subset of cpus, as well as only executing the tests on those cpus. + */ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwprobe.h" +#include "../../kselftest.h" + +#define MK_PREFETCH(fn) \ + le32_bswap(0 << 25 | (uint32_t)(fn) << 20 | 10 << 15 | 6 << 12 | 0 << 7 |= 19) + +static char mem[4096] __aligned(4096) =3D { [0 ... 4095] =3D 0xa5 }; + +static bool illegal; + +static void sigill_handler(int sig, siginfo_t *info, void *context) +{ + unsigned long *regs =3D (unsigned long *)&((ucontext_t *)context)->uc_mco= ntext; + uint32_t insn =3D *(uint32_t *)regs[0]; + + assert(insn =3D=3D MK_PREFETCH(regs[11])); + + illegal =3D true; + regs[0] +=3D 4; +} + +#define prefetch_insn(base, fn) \ +({ \ + asm volatile( \ + "mv a0, %0\n" \ + "li a1, %1\n" \ + ".4byte %2\n" \ + : : "r" (base), "i" (fn), "i" (MK_PREFETCH(fn)) : "a0", "a1", "memory");\ +}) + +static void prefetch_i(char *base) { prefetch_insn(base, 0); } + +static void prefetch_r(char *base) { prefetch_insn(base, 1); } + +static void prefetch_w(char *base) { prefetch_insn(base, 3); } + +static bool is_power_of_2(__u64 n) +{ + return n !=3D 0 && (n & (n - 1)) =3D=3D 0; +} + +static void test_no_zicbop(void *arg) +{ + // Zicbop prefetch.* are HINT instructions. + ksft_print_msg("Testing Zicbop instructions\n"); + + illegal =3D false; + prefetch_i(&mem[0]); + ksft_test_result(!illegal, "No prefetch.i\n"); + + illegal =3D false; + prefetch_r(&mem[0]); + ksft_test_result(!illegal, "No prefetch.r\n"); + + illegal =3D false; + prefetch_w(&mem[0]); + ksft_test_result(!illegal, "No prefetch.w\n"); +} + +static void test_zicbop(void *arg) +{ + struct riscv_hwprobe pair =3D { + .key =3D RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE, + }; + cpu_set_t *cpus =3D (cpu_set_t *)arg; + __u64 block_size; + long rc; + + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, = 0); + block_size =3D pair.value; + ksft_test_result(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_ZICBOP_= BLOCK_SIZE && + is_power_of_2(block_size), "Zicbop block size\n"); + ksft_print_msg("Zicbop block size: %llu\n", block_size); + + illegal =3D false; + prefetch_i(&mem[0]); + prefetch_r(&mem[0]); + prefetch_w(&mem[0]); + ksft_test_result(!illegal, "Zicbop prefetch.* on valid address\n"); + + illegal =3D false; + prefetch_i(NULL); + prefetch_r(NULL); + prefetch_w(NULL); + ksft_test_result(!illegal, "Zicbop prefetch.* on NULL\n"); +} + +static void check_no_zicbop_cpus(cpu_set_t *cpus) +{ + struct riscv_hwprobe pair =3D { + .key =3D RISCV_HWPROBE_KEY_IMA_EXT_0, + }; + cpu_set_t one_cpu; + int i =3D 0, c =3D 0; + long rc; + + while (i++ < CPU_COUNT(cpus)) { + while (!CPU_ISSET(c, cpus)) + ++c; + + CPU_ZERO(&one_cpu); + CPU_SET(c, &one_cpu); + + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_= cpu, 0); + assert(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_IMA_EXT_0); + + if (pair.value & RISCV_HWPROBE_EXT_ZICBOP) + ksft_exit_fail_msg("zicbop is only present on a subset of harts.\n" + "Use taskset to select a set of harts where zicbop\n" + "presence (present or not) is consistent for each hart\n"); + ++c; + } +} + +enum { + TEST_ZICBOP, + TEST_NO_ZICBOP, +}; + +enum { + HANDLER_SIGILL, + HANDLER_SIGSEGV, + HANDLER_SIGBUS, +}; + +static struct test_info { + bool enabled; + unsigned int nr_tests; + void (*test_fn)(void *arg); +} tests[] =3D { + [TEST_ZICBOP] =3D { .nr_tests =3D 3, test_zicbop }, + [TEST_NO_ZICBOP] =3D { .nr_tests =3D 3, test_no_zicbop }, +}; + +static struct sighandler_info { + const char *flag; + int sig; +} handlers[] =3D { + [HANDLER_SIGILL] =3D { .flag =3D "--sigill", .sig =3D SIGILL }, + [HANDLER_SIGSEGV] =3D { .flag =3D "--sigsegv", .sig =3D SIGSEGV }, + [HANDLER_SIGBUS] =3D { .flag =3D "--sigbus", .sig =3D SIGBUS }, +}; + +static bool search_flag(int argc, char **argv, const char *flag) +{ + int i; + + for (i =3D 1; i < argc; i++) { + if (!strcmp(argv[i], flag)) + return true; + } + return false; +} + +static void install_sigaction(int argc, char **argv) +{ + int i, rc; + struct sigaction act =3D { + .sa_sigaction =3D &sigill_handler, + .sa_flags =3D SA_SIGINFO, + }; + + for (i =3D 0; i < ARRAY_SIZE(handlers); ++i) { + if (search_flag(argc, argv, handlers[i].flag)) { + rc =3D sigaction(handlers[i].sig, &act, NULL); + assert(rc =3D=3D 0); + } + } + + if (search_flag(argc, argv, handlers[HANDLER_SIGILL].flag)) + tests[TEST_NO_ZICBOP].enabled =3D true; +} + +int main(int argc, char **argv) +{ + struct riscv_hwprobe pair; + unsigned int plan =3D 0; + cpu_set_t cpus; + long rc; + int i; + + install_sigaction(argc, argv); + + rc =3D sched_getaffinity(0, sizeof(cpu_set_t), &cpus); + assert(rc =3D=3D 0); + + ksft_print_header(); + + pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&cpus,= 0); + if (rc < 0) + ksft_exit_fail_msg("hwprobe() failed with %ld\n", rc); + assert(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_IMA_EXT_0); + + if (pair.value & RISCV_HWPROBE_EXT_ZICBOP) + tests[TEST_ZICBOP].enabled =3D true; + else + check_no_zicbop_cpus(&cpus); + + for (i =3D 0; i < ARRAY_SIZE(tests); ++i) + plan +=3D tests[i].enabled ? tests[i].nr_tests : 0; + + if (plan =3D=3D 0) + ksft_print_msg("No tests enabled.\n"); + else + ksft_set_plan(plan); + + for (i =3D 0; i < ARRAY_SIZE(tests); ++i) { + if (tests[i].enabled) + tests[i].test_fn(&cpus); + } + + ksft_finished(); +} --=20 2.47.2